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| HMS30C7202 highly-integrated mpu (arm based 32-bit microprocessor) datasheet version 1.4 hynix semiconductor inc.
HMS30C7202 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - ii - HMS30C7202 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - iii - copyright. 2002 hynix semiconductor inc. all rights reserved. no part of this publication may be copied in any form, by photocopy, microfilm, retrieval system, or by any other means now known or hereafter invented without the prior written permission of hynix semiconductor inc. hynix semiconductor inc. #1, hyangjeong-dong, heungduk-gu, cheongju- si, chungcheonbuk-do, republic of korea homepage: www.hynix.com technical support homepage: www.softonchip.com h.q. of hynix semiconductor inc . marketing site sales in korea telephone: 82-(0)43-270-4070 telephone: 82-(0)43-270-4085 telephone: 82-(0)2-3459-3843 facsimile: 82-(0)43-270-4099 facsimile: 82-(0)43-270-4099 facsimile: 82-(0)2-3459-3945 world wide sales network u.s.a. taiwan hong kong telephone: 1-408-232-8757 telephone: 886-(0)2-2500-8357 telephone: 852-2971-1640 facsimile: 1-408-232-8135 facsimile: 886 -(0)2-2509-8977 facsimile: 852-2971-1622 HMS30C7202 datasheet, ver1.4 may 12, 2004 HMS30C7202 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - iv - proprietary notice hynix logo is trademark of hynix semiconductor inc. neither the whole nor any part of the information containe d in, or the product described in, this document may be adapted or reproduced in any material from exce pts with the prior permission of the copyright holder. the product described in this document is subject to continuous developments and improvements. all particulars of the product and its use contained in this document are given by hynix in good faith. however, all warranties implied or expressed , including but not limit ed to implied warranties or merchantability, or fitness for purpose, are excluded. this document is intended only to assi st the reader in the us e of the product. hynix semiconductor inc. shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect us e of the product. hynix semiconductor inc. may make changes to specification and product description at any time without notice. change log issue date by change a-01 2002/08/27 kisun kim the first draft a-02 2002/08/28 kisun kim pmu freq. range / qfp footprint / bga pin diagram a-03 2002/10/01 kisun kim pkg soldering condition / harry?s update a-04 2002/10/05 kisun kim ca n interrupt desc. / interrupt controller fiq desc. a-05 2002/10/14 kisun kim harry?s review (chapter 1~5) a-06 2002/12/28 kisun kim harry?s review (chapter 6~11) a-07 2003/01/09 kisun kim smi example / smc / usb a-08 2003/02/26 injae koo dc electrical characteristics / rtc / usb a-10 2003/03/03 injae koo the first release (version 1.0) a-11 2003/03/28 injae koo lcd / can / overview / dc e. char. / gpio (version 1.1) a-12 2003/06/03 injae koo dma / dc char. / gpio / delete the i2s (version 1.2) a-13 2003/09/15 injae koo errata(version 1.0) is incorporated into this version a-14 2004/05/12 injae koo adc/gpio/sdramc/mmc/lcd/ac characteristics (smi) HMS30C7202 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - v - features ? 32-bit arm7tdmi risc static cmos cpu core : running up to 70 mhz ? 8kbytes combined instruction/data cache ? memory management unit ? supports little endian operating system ? 2kbytes sram for internal buffer memory ? on-chip peripherals with individual power-down: - multi-channel dma - 4 timer channels with watch dog timer - intelligent interrupt controller - memory controller for rom, flash, sram, sdram - power management unit - lcd controller for mono/color stn and tft lcd - real-time clock (32.768khz oscillator) - infrared communications (sir support) - 4 uarts (16c550 compatible) - ps/2 external keyboard / mouse interface - 2 pulse-width-modulated (pwm) interface - matrix keyboard control interface (8*8) - gpio - mmc / smc card interface - 2 controller area network (can) - usb (slave) - on-chip adc and interface module (battery check, audio in, touch panel) - on-chip dac and interface module (8 bit stereo audio output) - 3 plls figure a. functional block diagram ? jtag debug interface and boundary scan ? 0.25um low power cmos process ? 2.5v internal / 3.3v io supply voltage ? 256-pin mqfp / fbga package ? low power consumption HMS30C7202 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - vi - overview the HMS30C7202 is a highly integrated low power micr oprocessor for personal digital assistants, and other applications described below. the device incorporat es an arm720t cpu and system interface logic to interface with various types of devices. HMS30C7202 is a highly modular design based on the amba bus architecture between cpu and internal modules. the on-chip peripherals include lcd controller with dma support for external sdram memory, analog functions such as adc, dac, and plls. intelligent interru pt controller and internal 2kbytes sram can support an efficient interrupt service executio n. the HMS30C7202 also supports voice recording, sound playback and a touch panel interface. uart, u sb, ps2 and can provide serial communication channels for external systems. the power management featur es result in very low power cons umption. the HMS30C7202 provides an excellent solution for personal digital assistants (pdas), and data terminal running the microsoft windows ce operating system. other applicati ons include smart phones, internet appliances, telematic systems and embedded computer. figure b. system configuration HMS30C7202 1 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 1 - table of contents 1 architectural overvi ew ......................................................................................................... .................. 9 1.1 p rocessor ............................................................................................................................... ............................. 9 1.2 v ideo ............................................................................................................................... .................................... 9 1.3 m emory ............................................................................................................................... ................................ 9 1.4 i nternal b us s tructure ............................................................................................................................... ..... 9 1.4.1 asb............................................................................................................................ ................................... 9 1.4.2 video bus ...................................................................................................................... ................................ 9 1.4.3 apb ............................................................................................................................ .................................. 9 1.5 sdram c ontroller ............................................................................................................................... ......... 10 1.6 p eripheral dma............................................................................................................................ ................... 10 1.6.1 overview....................................................................................................................... .............................. 10 1.6.2 transfer sizes................................................................................................................. ............................. 10 1.6.3 fly-by ......................................................................................................................... ................................ 10 1.6.4 timing......................................................................................................................... ................................ 11 1.6.5 sound out put................................................................................................................... ............................ 11 1.7 p eripherals ............................................................................................................................... ........................ 11 1.8 p ower management ............................................................................................................................... .......... 11 1.8.1 clock ga ting ................................................................................................................... ............................ 12 1.8.2 pmu ............................................................................................................................ ............................... 12 1.9 t est and debug ............................................................................................................................... .................. 12 2 pin description ................................................................................................................ ................................ 13 2.1 256-p in d iagram ............................................................................................................................... ................ 13 2.1.1 mqfp type ..................................................................................................................... ........................... 13 2.1.2 fbga type ...................................................................................................................... ........................... 15 2.2 p in d escriptions ............................................................................................................................... ................ 17 2.2.1 external signa l func tions ...................................................................................................... .................... 17 2.2.2 multiple func tion pins ......................................................................................................... ...................... 20 2.2.2.1 port a ......................................................................................................................... ......................... 20 2.2.2.2 port b ......................................................................................................................... ......................... 20 2.2.2.3 port c ......................................................................................................................... ......................... 21 2.2.2.4 port d ......................................................................................................................... ......................... 21 2.2.2.5 port e......................................................................................................................... .......................... 22 2.2.2.6 usb transceiver test & analog test ............................................................................................. ........ 23 2.2.2.7 dma............................................................................................................................ ........................... 23 2.2.2.8 inverter chain................................................................................................................. ........................ 23 3 arm720t m acroc ell.............................................................................................................. ......................... 24 3.1 arm720t m acrocell ............................................................................................................................... ....... 24 4 memory map ..................................................................................................................... .................................. 25 5 pmu & pll...................................................................................................................... ........................................ 27 5.1 b lock f unctions ............................................................................................................................... ............... 27 5.2 p ower management ............................................................................................................................... .......... 28 5.2.1 state di agram.................................................................................................................. ........................... 28 5.2.2 power manageme nt st ates ........................................................................................................ .................. 28 5.2.3 wake-up debounce and interrupt................................................................................................. .............. 29 5.3 r egisters ............................................................................................................................... ............................ 30 5.3.1 pmu mode regist er (pmumode) .................................................................................................... ....... 30 5.3.2 pmu id regist er (pmuid)........................................................................................................ ................ 30 5.3.3 pmu reset /pll status register (pmustat)....................................................................................... ..... 30 5.3.4 pmu clock control re gister (pmuclk) ............................................................................................ ...... 32 5.3.5 pmu debounce counter test register (p mudbct )................................................................................. 33 5.3.6 pmu pll test register (pmuplltr)............................................................................................... ........ 33 5.4 t imings ............................................................................................................................... ............................... 34 HMS30C7202 2 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 2 - 5.4.1 reset sequences of power on reset.............................................................................................. ............. 34 5.4.2 software generate d warm reset .................................................................................................. .............. 35 5.4.3 an externally gene rated warm reset ............................................................................................. ............ 35 6 sdram co ntro ller............................................................................................................... ......................... 37 6.1 s upported m emory d evices ............................................................................................................................ 37 6.2 r egisters ............................................................................................................................... ........................... 38 6.2.1 sdram controller configurat ion register (sdcon) ............................................................................... 3 8 6.2.2 sdram controller refresh timer register (sdref) ................................................................................ 40 6.2.3 sdram controller write buffer fl ush timer regist er (sdwbf)................................................................. 40 6.2.4 sdram controller wait dr iver register (sdwait) ................................................................................. .40 6.3 p ower - up i nitialization of the sdram s ....................................................................................................... 40 6.4 sdram m emory m ap ............................................................................................................................... ....... 41 6.5 amba a ccesses and a rbitration .................................................................................................................. 42 6.6 m erging w rite b uffer ............................................................................................................................... ..... 42 7 static memory interface........................................................................................................ .................. 44 7.1 e xternal s ignals ............................................................................................................................... .............. 44 7.2 f unctional d escription ............................................................................................................................... ... 44 7.2.1 memory bank select............................................................................................................. ....................... 44 7.2.2 access sequencing .............................................................................................................. ........................ 44 7.2.3 wait states generation ......................................................................................................... ....................... 45 7.2.4 burst read control............................................................................................................. .......................... 45 7.2.5 byte lane wr ite control ........................................................................................................ ....................... 45 7.3 r egisters ............................................................................................................................... ........................... 46 7.3.1 mem configura tion regi ster ..................................................................................................... ................ 46 7.4 e xamples of the smi r ead , w rite wait timing diagram .............................................................................. 47 7.4.1 read normal wait (non- sequential mode)......................................................................................... ......... 47 7.4.2 read normal wait (se quential mode) ............................................................................................. ............ 48 7.4.3 read burst wait (se quential mode).............................................................................................. ............... 49 7.4.4 write normal wait (s equential mode) ............................................................................................ ............. 50 7.5 i nternal sram ........................................................................................................................... ..................... 51 7.5.1 remapping enable regi ster ...................................................................................................... ................. 51 7.5.2 remap source addr ess regi ster .................................................................................................. ............... 51 8 lcd cont roller ................................................................................................................. ............................. 52 8.1 v ideo operation ............................................................................................................................... ................ 52 8.1.1 lcd dat apath................................................................................................................... .......................... 53 8.1.1.1 palette ram & 16bpp m ode ....................................................................................................... ........... 53 8.1.2 color/grayscal e dithering...................................................................................................... ................... 55 8.1.3 how to order the bi t on ld[7 :0] output ......................................................................................... ............ 55 8.1.4 tft mode ....................................................................................................................... ............................ 56 8.2 r egisters ............................................................................................................................... ........................... 56 8.2.1 lcd power control .............................................................................................................. ..................... 56 8.2.2 lcd controller status/mask and interrupt registers ............................................................................. ... 57 8.2.3 lcd dma base address register .................................................................................................. ............ 58 8.2.4 lcd dma channel curren t address register ....................................................................................... .... 58 8.2.5 lcd timing 0 register.......................................................................................................... ..................... 58 8.2.6 lcd timing 1 register.......................................................................................................... ..................... 59 8.2.7 lcd timing 2 register.......................................................................................................... ..................... 60 8.2.8 lcd test register.............................................................................................................. ......................... 61 8.2.9 grayscaler test registers ...................................................................................................... ..................... 61 8.2.10 lcd palette registers .......................................................................................................... ....................... 62 8.3 t imings ............................................................................................................................... ............................... 63 9 fast amba peripherals .......................................................................................................... ...................... 64 9.1 dma c ontroller ............................................................................................................................... .............. 64 9.1.1 external signals ............................................................................................................... .......................... 64 9.1.2 registers...................................................................................................................... ............................... 64 9.1.2.1 adr0 ........................................................................................................................... .......................... 65 HMS30C7202 3 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 3 - 9.1.2.2 asr ............................................................................................................................ ............................ 65 9.1.2.3 tnr0........................................................................................................................... ........................... 65 9.1.2.4 tsr............................................................................................................................ ............................. 65 9.1.2.5 ccr0........................................................................................................................... ........................... 65 9.1.2.6 adr1 ........................................................................................................................... .......................... 66 9.1.2.7 tnr1........................................................................................................................... ........................... 66 9.1.2.8 ccr1........................................................................................................................... ........................... 66 9.1.2.9 adr2 ........................................................................................................................... .......................... 66 9.1.2.10 tnr2 ........................................................................................................................... ....................... 66 9.1.2.11 ccr2 ........................................................................................................................... ....................... 67 9.1.2.12 flagr.......................................................................................................................... ..................... 67 9.1.2.13 dmaor .......................................................................................................................... ................... 67 9.1.3 dmac operation ................................................................................................................. ....................... 68 9.2 mmc/ spi c ontroller ............................................................................................................................... ...... 69 9.2.1 external signals............................................................................................................... ........................... 69 9.2.2 registers (s pi mode)........................................................................................................... ....................... 69 9.2.2.1 spimmc control re gister (spicr)................................................................................................ ....... 69 9.2.2.2 spimmc status register (spisr)................................................................................................. ......... 70 9.2.2.3 spimmc xch counter re gister (x chcnt) ....................................................................................... 70 9.2.2.4 spimmc tx data buffer register (txbuff)...................................................................................... 70 9.2.2.5 spimmc rx data buffer register (rxbuff) ..................................................................................... 70 9.2.2.6 spimmc reset regist er (resetreg)............................................................................................... ....... 71 9.2.3 timings ........................................................................................................................ ............................... 71 9.2.4 spi operatio n for mmc .......................................................................................................... ................... 72 9.2.5 multimedia card ho st controller................................................................................................ ............... 73 9.2.6 registers ...................................................................................................................... ............................... 73 9.2.6.1 mmc mode register.............................................................................................................. ................ 73 9.2.6.2 mmc operatio n register ......................................................................................................... .............. 74 9.2.6.3 mmc status register ............................................................................................................ ................. 74 9.2.6.4 mmc interrupt en able register .................................................................................................. ........... 75 9.2.6.5 mmc block size register........................................................................................................ .............. 76 9.2.6.6 mmc block numb er register...................................................................................................... .......... 76 9.2.6.7 mmc time peri od regi ster....................................................................................................... ............. 76 9.2.6.8 mmc command buff er register .................................................................................................... ....... 76 9.2.6.9 mmc argument buff er register ................................................................................................... ......... 76 9.2.6.10 mmc response buff er register................................................................................................... ...... 77 9.2.6.11 mmc data buffer register ....................................................................................................... ......... 77 9.2.6.12 mmc ready timeout register..................................................................................................... ...... 77 9.2.7 basic operation in mmc mode.................................................................................................... .............. 77 9.2.7.1 write operation ................................................................................................................ ...................... 78 9.2.7.2 read operation................................................................................................................. ...................... 78 9.3 smc c ontroller ............................................................................................................................... ............... 79 9.3.1 external signals............................................................................................................... ........................... 79 9.3.2 registers ...................................................................................................................... ............................... 79 9.3.2.1 smc command regi ster (smccmd) .................................................................................................. .79 9.3.2.2 smc address regi ster (smcadr) .................................................................................................. ..... 80 9.3.2.3 smc data write regi ster (smcdatw).............................................................................................. .. 80 9.3.2.4 smc data read regi ster (smcdatr)............................................................................................... ... 81 9.3.2.5 smc configuration re gister (smcconf)........................................................................................... .81 9.3.2.6 smc timing parameter re gister (smctime) ...................................................................................... 82 9.3.2.7 smc status regist er (smcstat).................................................................................................. ........ 82 9.4 s ound i nterface ............................................................................................................................... ................ 84 9.4.1 external signals............................................................................................................... ........................... 84 9.4.2 registers ...................................................................................................................... ............................... 84 9.4.2.1 scont.......................................................................................................................... ......................... 84 9.4.2.2 sdadr .......................................................................................................................... ........................ 85 9.5 usb s lave i nterface ............................................................................................................................... ........ 86 9.5.1 block di agram .................................................................................................................. ......................... 87 9.5.2 theory of operation ............................................................................................................ ....................... 87 9.5.3 endpoint fifos (rx, tx) ........................................................................................................ .................... 90 HMS30C7202 4 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 4 - 9.5.4 external signals ............................................................................................................... .......................... 90 9.5.5 registers...................................................................................................................... ............................... 90 9.5.5.1 gctrl.......................................................................................................................... ......................... 90 9.5.5.2 epctrl......................................................................................................................... ........................ 90 9.5.5.3 intmask........................................................................................................................ ...................... 91 9.5.5.4 intstat........................................................................................................................ ........................ 91 9.5.5.5 pwr ............................................................................................................................ ........................... 92 9.5.5.6 devid .......................................................................................................................... ......................... 92 9.5.5.7 devclass ....................................................................................................................... .................... 92 9.5.5.8 intclass....................................................................................................................... ...................... 92 9.5.5.9 setup0 / setup1 ................................................................................................................ ................ 94 9.5.5.10 endp0rd........................................................................................................................ .................. 94 9.5.5.11 endp0wt ........................................................................................................................ ................. 94 9.5.5.12 endp1rd........................................................................................................................ .................. 94 9.5.5.13 endp2wt ........................................................................................................................ ................. 94 10 slow amba pe ripherals .......................................................................................................... ................ 95 10.1 adc i nterface c ontroller ............................................................................................................................ 95 10.1.1 external signals ............................................................................................................... .......................... 95 10.1.2 registers...................................................................................................................... ............................... 95 10.1.2.1 adc control regi ster ( adccr)................................................................................................... .... 96 10.1.2.2 adc touch panel control register ( adctpcr).............................................................................. 96 10.1.2.3 adc battery check contro l register (adcba cr)........................................................................... 97 10.1.2.4 adc sound control regi ster (adc sdcr) ....................................................................................... 97 10.1.2.5 adc interrupt status register (adcisr)......................................................................................... .97 10.1.2.6 adc tip down control status register ( adctdcs r) .................................................................... 98 10.1.2.7 adc direct control re gister (a dcdircr) ..................................................................................... 98 10.1.2.8 adc direct data read re gister (adcdirdata)............................................................................ 98 10.1.2.9 adc 1 st touch panel data register.................................................................................................... 9 9 10.1.2.10 adc 2 nd touch panel da ta register ................................................................................................. 99 10.1.2.11 adc main battery data re gister (adcmbdata) ........................................................................ 100 10.1.2.12 adc backup battery data register ( adcbbdat a)...................................................................... 100 10.1.2.13 adc sound data register ( adcsdata0 ? adc sdata7 )........................................................... 100 10.2 can i nterface ............................................................................................................................... ................ 102 10.2.1 block di agram .................................................................................................................. ....................... 103 10.2.2 register map ................................................................................................................... ......................... 103 10.2.3 registers...................................................................................................................... ............................. 104 10.2.3.1 can control register ........................................................................................................... ........... 104 10.2.3.2 can status register............................................................................................................ ............. 105 10.2.3.3 can error coun ting register .................................................................................................... ...... 105 10.2.3.4 can bit timi ng regi ster........................................................................................................ ......... 106 10.2.3.5 can interrupt register ......................................................................................................... ........... 106 10.2.3.6 can test register.............................................................................................................. .............. 106 10.2.3.7 can brp extens ion regi ster ..................................................................................................... ..... 107 10.2.3.8 can enable register ............................................................................................................ ........... 107 10.2.3.9 interface x command re quest register .......................................................................................... 1 07 10.2.3.10 interface x command mask register .............................................................................................. 107 10.2.3.11 interface x mask 1 register.................................................................................................... ......... 108 10.2.3.12 interface x mask 2 register.................................................................................................... ......... 108 10.2.3.13 interface x arbitr ation 1 register ............................................................................................. ....... 109 10.2.3.14 interface x arbitr ation 2 register ............................................................................................. ....... 109 10.2.3.15 interface x message control re gister........................................................................................... ... 109 10.2.3.16 interface x data a1 register................................................................................................... ..........110 10.2.3.17 interface x data a2 register................................................................................................... ..........110 10.2.3.18 interface x data b1 register................................................................................................... ..........110 10.2.3.19 interface x data b2 register................................................................................................... ..........111 10.2.3.20 transmission reque st 1 register................................................................................................ .......111 10.2.3.21 transmission reque st 2 register................................................................................................ .......111 10.2.3.22 new data 1 register............................................................................................................ ..............111 10.2.3.23 new data 2 register............................................................................................................ ..............111 HMS30C7202 5 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 5 - 10.2.3.24 interrupt pending 1 register ................................................................................................... .......... 112 10.2.3.25 interrupt pending 2 register ................................................................................................... .......... 112 10.2.3.26 message valid 1 register....................................................................................................... ........... 112 10.2.3.27 message valid 2 register....................................................................................................... ........... 112 10.3 gpio ........................................................................................................................... ..................................... 114 10.3.1 external signals............................................................................................................... ......................... 114 10.3.2 registers ...................................................................................................................... ............................. 114 10.3.2.1 adata.......................................................................................................................... ................... 115 10.3.2.2 adir ........................................................................................................................... ..................... 115 10.3.2.3 amask.......................................................................................................................... .................. 116 10.3.2.4 astat.......................................................................................................................... .................... 116 10.3.2.5 aedge .......................................................................................................................... .................. 116 10.3.2.6 aclr ........................................................................................................................... .................... 116 10.3.2.7 apol........................................................................................................................... ..................... 116 10.3.2.8 gpio port a enable register .................................................................................................... .... 116 10.3.2.9 bdata .......................................................................................................................... ................... 117 10.3.2.10 bdir ........................................................................................................................... ..................... 117 10.3.2.11 bmask.......................................................................................................................... .................. 117 10.3.2.12 bstat .......................................................................................................................... .................... 117 10.3.2.13 bedge.......................................................................................................................... ................... 117 10.3.2.14 bclk ........................................................................................................................... .................... 117 10.3.2.15 bpol........................................................................................................................... ..................... 117 10.3.2.16 gpio port b enable register .................................................................................................... .... 117 10.3.2.17 cdata .......................................................................................................................... ................... 117 10.3.2.18 cdir ........................................................................................................................... ..................... 117 10.3.2.19 cmask.......................................................................................................................... .................. 118 10.3.2.20 cbstat ......................................................................................................................... .................. 118 10.3.2.21 cedge.......................................................................................................................... ................... 118 10.3.2.22 cclk ........................................................................................................................... .................... 118 10.3.2.23 cpol........................................................................................................................... ..................... 118 10.3.2.24 gpio port c enable register .................................................................................................... .... 118 10.3.2.25 ddata.......................................................................................................................... ................... 118 10.3.2.26 ddir ........................................................................................................................... ..................... 118 10.3.2.27 dmask.......................................................................................................................... .................. 118 10.3.2.28 dbstat ......................................................................................................................... .................. 118 10.3.2.29 dedge .......................................................................................................................... .................. 118 10.3.2.30 dclk ........................................................................................................................... .................... 118 10.3.2.31 dpol........................................................................................................................... ..................... 118 10.3.2.32 gpio port d enable register.................................................................................................... .... 118 10.3.2.33 edata .......................................................................................................................... ................... 119 10.3.2.34 edir........................................................................................................................... ...................... 119 10.3.2.35 emask .......................................................................................................................... .................. 119 10.3.2.36 ebstat......................................................................................................................... ................... 119 10.3.2.37 eedge.......................................................................................................................... ................... 119 10.3.2.38 eclk........................................................................................................................... ..................... 119 10.3.2.39 epol ........................................................................................................................... ..................... 119 10.3.2.40 gpio port e enable register .................................................................................................... .... 119 10.3.2.41 tic test mode register(tictmdr) ................................................................................................ .119 10.3.2.42 porta multi-function select register(a mulsel)......................................................................... 120 10.3.2.43 swap pin configuratio n registe r(swap)....................................................................................... 120 10.3.3 gpio in terrupt ................................................................................................................. ........................ 120 10.3.4 gpio rise/fall time ............................................................................................................ .................... 121 10.4 i nterrupt c ontroller ............................................................................................................................... .... 122 10.4.1 block di agram .................................................................................................................. ........................ 122 10.4.2 registers ...................................................................................................................... ............................. 122 10.4.2.1 interrupt enable register (ier) ................................................................................................ ........ 123 10.4.2.2 interrupt status register (isr)................................................................................................ .......... 124 10.4.2.3 irq vector re gister (ivr) ...................................................................................................... ......... 125 10.4.2.4 source vector register (svr0 to svr30)........................................................................................ 1 25 10.4.2.5 interrupt id re gister (idr) .................................................................................................... .......... 125 HMS30C7202 6 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 6 - 10.4.2.6 priority set register (psr0 to psr7)........................................................................................... .... 125 10.5 m at r i x k eyboard i nterface c ontroller ................................................................................................... 127 10.5.1 external signals ............................................................................................................... ........................ 127 10.5.2 registers...................................................................................................................... ............................. 127 10.5.2.1 keyboard configuratio n register (kbcr) ...................................................................................... 128 10.5.2.2 keyboard scanout registe r(kbsc) ................................................................................................ . 128 10.5.2.3 keyboard test re gister (kbtr) .................................................................................................. .... 129 10.5.2.4 keyboard value re gister (kvr0) ................................................................................................. ... 129 10.5.2.5 keyboard value re gister (kvr1) ................................................................................................. ... 129 10.5.2.6 keyboard status register (kbsr) ................................................................................................ ... 129 10.6 ps/2 i nterface c ontroller ........................................................................................................................... 131 10.6.1 external signals ............................................................................................................... ........................ 131 10.6.2 registers...................................................................................................................... ............................. 131 10.6.2.1 psdata ......................................................................................................................... .................. 131 10.6.2.2 psstat ......................................................................................................................... ................... 132 10.6.2.3 psconf......................................................................................................................... .................. 132 10.6.2.4 psintr ......................................................................................................................... ................... 133 10.6.2.5 pstdlo......................................................................................................................... .................. 133 10.6.2.6 pstpri......................................................................................................................... .................... 133 10.6.2.7 pstxmt ......................................................................................................................... ................. 134 10.6.2.8 pstrec ......................................................................................................................... .................. 134 10.6.2.9 pspwdn......................................................................................................................... ................. 135 10.6.3 applicati on note s .............................................................................................................. ....................... 135 10.7 rtc ............................................................................................................................ ...................................... 136 10.7.1 external signals ............................................................................................................... ........................ 137 10.7.2 functional de scription......................................................................................................... .................... 137 10.7.3 registers...................................................................................................................... ............................. 137 10.7.3.1 rtc data regist er (rtcdr) ...................................................................................................... ..... 137 10.7.3.2 rtc match regist er (rtcmr)..................................................................................................... ... 138 10.7.3.3 rtc status regi ster (rtcs) ..................................................................................................... ....... 138 10.7.3.4 rtc control regi ster (r tccr)................................................................................................... .... 138 10.8 timer .......................................................................................................................... ................................... 139 10.8.1 external signals ............................................................................................................... ........................ 139 10.8.2 registers...................................................................................................................... ............................. 139 10.8.2.1 timer [0,1,2] base regi ster (t[0,1,2]base) ................................................................................... 13 9 10.8.2.2 timer [0,1,2] count regi ster (t[0,1 ,2]count ).............................................................................. 140 10.8.2.3 timer [0,1,2] control regi ster (t[0,1 ,2]ctrl)............................................................................... 140 10.8.2.4 timer top-level control register (t opctrl)................................................................................ 140 10.8.2.5 timer status regi ster (topstat) ................................................................................................ ... 141 10.8.2.6 timer lower 32-bit count register of 64-bit coun ter (t64l ow) .................................................. 141 10.8.2.7 timer upper 32-bit count register of 64-bit coun ter (t64h igh) .................................................. 141 10.8.2.8 timer 64-bit counter contro l register (t64ctr l)......................................................................... 141 10.8.2.9 timer 64-bit counter test register (t64tr) ................................................................................... 14 1 10.8.2.10 timer lower 32-bit base register of 64-bit counte r (t64lba se)................................................. 142 10.8.2.11 timer upper 32-bit base register of 64-bit counte r (t64hba se)................................................. 142 10.8.2.12 pwm channel [0,1] count re gister (p[0 ,1]count )...................................................................... 142 10.8.2.13 pwm channel [0,1] width re gister (p[0,1 ]width) ...................................................................... 143 10.8.2.14 pwm channel [0,1] period re gister (p[0,1 ]period) .................................................................... 143 10.8.2.15 pwm channel [0,1] control register (p[0 ,1]ctrl)....................................................................... 143 10.8.2.16 pwm channel[0,1] test re gister(p[0,1 ]pwmtr) .......................................................................... 143 10.9 uart/sir....................................................................................................................... ................................. 144 10.9.1 external signals ............................................................................................................... ........................ 144 10.9.2 registers...................................................................................................................... ............................. 145 10.9.2.1 rbr/thr/ dll .................................................................................................................... ............ 146 10.9.2.2 ier/dlm ........................................................................................................................ ................. 146 10.9.2.3 iir/fcr........................................................................................................................ .................... 146 10.9.2.4 lcr ............................................................................................................................ ...................... 148 10.9.2.5 mcr............................................................................................................................ ..................... 149 10.9.2.6 lsr ............................................................................................................................ ...................... 150 10.9.2.7 msr ............................................................................................................................ ..................... 151 HMS30C7202 7 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 7 - 10.9.2.8 scr ............................................................................................................................ ...................... 152 10.9.2.9 uarten ......................................................................................................................... ..................... 152 10.9.3 fifo interrupt m ode operation .................................................................................................. ............ 152 10.10 w atchdog t imer ............................................................................................................................... .......... 154 10.10.1 watchdog timer opera tion....................................................................................................... ............ 154 10.10.1.1 the watchdog timer mode ........................................................................................................ ...... 154 10.10.1.2 the interval timer mode........................................................................................................ .......... 154 10.10.1.3 timing of setting the overflo w flag ............................................................................................ ...... 155 10.10.1.4 timing of clearing the overflo w flag ........................................................................................... ..... 155 10.10.2 registers ...................................................................................................................... ......................... 155 10.10.2.1 wdt control regist er (wdtctrl) ............................................................................................... 15 5 10.10.2.2 wdt status register (wdtstat) .................................................................................................. 156 10.10.2.3 wdt counter (wdtcn t)........................................................................................................... .... 156 10.10.3 examples of re gister setting ................................................................................................... ............. 157 10.10.3.1 interval ti mer mode ............................................................................................................ ............. 157 10.10.3.2 watchdog timer mode with in ternal reset disabl e ......................................................................... 157 10.10.3.3 watchdog timer mode with manual reset ...................................................................................... 158 11 debug and test inter face ....................................................................................................... ............ 159 11.1 o verview ............................................................................................................................... .......................... 159 11.2 s oftware d evelopment d ebug and t est i nterface ................................................................................... 159 11.3 t est a ccess p ort and b oundary -s can ......................................................................................................... 159 11.3.1 reset .......................................................................................................................... ............................... 160 11.3.2 pull up re sistors.............................................................................................................. ......................... 160 11.3.3 instruction register ........................................................................................................... ....................... 161 11.3.4 public inst ructions............................................................................................................ ........................ 161 11.3.5 test data registers ............................................................................................................ ....................... 163 11.3.6 boundary scan inte rface si gnals................................................................................................ .............. 164 11.4 p roduction t est f eatures ............................................................................................................................ 172 12 electrical ch aracteris tics ..................................................................................................... ....... 173 12.1 a bsolute m aximum r atings ......................................................................................................................... 173 12.2 dc characteristics ............................................................................................................................... ........ 174 12.3 a/d c onverter e lectrical c haracteristics .............................................................................................. 175 12.4 d/a c onverter e lectrical c haracteristics .............................................................................................. 176 12.5 ac c haracteristics ............................................................................................................................... ........ 177 12.5.1 static memory interface ........................................................................................................ ................... 177 12.5.1.1 read access ti ming (singl e mode)...................................................................................... ............... 177 12.5.1.2 read access ti ming (burst mode) ....................................................................................... ............... 178 12.5.1.3 write access timing ................................................................................................... ........................ 179 12.5.2 sdram inte rface................................................................................................................ ...................... 180 12.5.3 lcd interface.................................................................................................................. ......................... 181 12.5.4 uart(universal asynchronous receiver trans mitter) ............................................................................ 18 3 12.6 p ackage ............................................................................................................................... ............................ 184 12.6.1 recommended solder ing condi tions ............................................................................................... ......... 184 12.6.1.1 mqfp(metric quad flat pack ) type.............................................................................................. . 184 12.6.1.2 fbga(chip array ball gr id array) type......................................................................................... 1 84 12.6.2 pictures of pa ckage marking .................................................................................................... ............... 185 13 appendix ....................................................................................................................... .................................. 186 13.1 d eep - sleep , w ake - up i ssues of HMS30C7202 pmu...................................................................................... 186 13.1.1 wake-up ........................................................................................................................ ............................ 186 13.1.2 deep-sleep ..................................................................................................................... ........................... 186 HMS30C7202 8 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 8 - list of figures figure 5-1 pmu power ma nagement stat e diagr am........................................................................ 28 figure 5-2 pmu co ld rese t event ............................................................................................... .... 34 figure 5-3 pmu software generated wa rm rese t........................................................................... 35 figure 5-4 pmu an external ly generated warm rese t .................................................................... 36 figure 6-1 sdram controller software example and memory operation diagram ......................... 39 figure 8-1 video sy stem blo ck diagr am ......................................................................................... .52 figure 8-2 5:6:5 comb ination of 16bpp da ta.................................................................................... 53 figure 8-3 palette ram entrie s for 5:6:5 co mbinatio n ..................................................................... 54 figure 8-4 sample code for 5:6:5 palette generatio n...................................................................... 54 figure 8-5 lcd palette word bit field fo r stn m ode ...................................................................... 62 figure 8-6 lcd palette word bit field fo r tft m ode ....................................................................... 62 figure 8-7 example mono stn l cd panel signal waveform s ........................................................ 63 figure 8-8 example tft signal waveforms, start of fram e ............................................................ 63 figure 8-9 example tft signal waveforms, end of last li ne ......................................................... 63 figure 9-1 usb block dia gram.................................................................................................. ....... 87 figure 9-2 usb serial interfac e engi ne........................................................................................ .... 88 figure 9-3 usb device inte rface device controlle r.......................................................................... 89 figure 10-1 typica l can ne twork............................................................................................... .....102 figure 10-2 block dia gram of the can......................................................................................... ..103 figure 10-3 interrupt c ontroller blo ck diagram ................................................................................ .122 figure10-4 a flow chart of the keyboard contro ller............................................................................1 27 figure 10-5 ps/2 controller tr ansmitting data ti ming diagr am ...................................................... 133 figure 10-6 ps/2 controller re ceiving data ti ming diagr am..........................................................134 figure 10-7 rt c connec tion .................................................................................................... .......136 figure 10-8 rtc block di agram................................................................................................. .....137 figure 10-9 wdt operation in the watchdog timer m ode .............................................................. 154 figure 10-10 wdt oper ation in the interv al timer mode ................................................................155 figure 10-11 interrupt clear in the interval timer m ode.................................................................... 157 figure 10-12 interrupt clear in the watc hdog timer mode with reset di sable ...................................158 figure 10-13 interrupt clear in the watc hdog timer mode with manual reset ...................................158 list of tables table 2-1 pin signa l type defi nition ........................................................................................... ....... 17 table 2-2 external signal fu nctions ............................................................................................ ...... 19 table 4-1 top-leve l addre ss map ................................................................................................ ....... 25 table 4-2 peripheral s base ad dresses ........................................................................................... ... 26 table 5-1 pmu regi ster summary ................................................................................................. ... 30 table 5-2 pmu bit settings for a cold re set event within pm ustat regi ster.................................. 35 table 5-3 pmu bit settings for a software gener ated warm reset within pmustat register ........ 35 table 5-4 pmu bit settings for a warm reset within pmus tat regi ster ......................................... 36 table 6-1 sdram controll er register summary............................................................................... 38 table 6-2 sdram row/co lumn addre ss map................................................................................... 41 table 6-3 sdram de vice sele ction ............................................................................................... ... 42 table 7-1 static memory c ontroller regist er summa ry ..................................................................... 46 table 8-1 lcd colorgra yscale intensities and modulation rates........................................................ 55 table 8-2 how to order the bit on ld [7:0] in 8-bit co lor stn mode .................................................... 56 table 8-3 lcd controller register summary..................................................................................... 5 6 table 9-1 dma controller register summary .................................................................................... 65 table 10-1 adc controller register summary .................................................................................. 95 table 10-2 interrupt cont roller conf iguration.................................................................................. ...122 table 10-3 interrupt contro ller register summary ............................................................................123 table 10-4 matrix keyboard interfac e controller regi ster summary................................................128 table 10-5 ps/2 controlle r register summary .................................................................................131 table 10-6 non-amba signals wi thin rtc core bloc k.....................................................................136 table 10-7 rtc r egister summary ................................................................................................ ..137 table 10-8 timer r egister summary .............................................................................................. ..139 table 10-9 uart/sir register summary.........................................................................................14 6 table 10-10 baud rate with decimal di visor at 3.6864mhz cr ystal freque ncy ...............................149 table 10-11 watchdog time r register summary..............................................................................155 HMS30C7202 9 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 9 - 1 architectural overview 1.1 processor the arm720t core incorporates an 8k unified write-th rough cache, and an 8 data entry, 4-address entry write buffer. it also incorporates an mmu with a 64 entry tlb, and wince enhancements. 1.2 video the integrated lcd controller can c ontrol stn displays and tft displays, up to 640x480 (vga) resolution and 16bit color. on mono displays it can directly generate 16 gray scales. 1.3 memory HMS30C7202 incorporates two independent memory cont rollers. a high-speed 16-bit wide interface connects directly to one or two 16, 64,128 or 256mbit sdram devices, supporting dram memory sizes in the range 2 to 64mb. a separate 32- bit data path interfaces to rom or flash devices. burst mode roms are supported, for increased performance, allowing operating system code to be executed directly from rom. since the rom and sdram interfaces are independent, the processor core can execute rom code simultaneously with video dma access to the sdram, thus increasing to tal effective memory bandwidth, and hence overall performance. 1.4 internal bus structure the HMS30C7202 internal bus organization is bas ed upon the amba standard, but with some minor modifications to the peripheral buses (the apbs). there are three main buses in the HMS30C7202: 1. the main system bus (the asb) to which the cpu and memory controllers are connected 2. the fast apb to which high-band width peripherals are connected 3. the slow apb (to which timers, the uart and ot her low-bandwidth peripherals are connected) there is also a separate video dma bus. 1.4.1 asb the asb is designed to allow the arm continuous a ccess to both, the rom and the sdram interface. the sdram controller straddles both the asb and the video dma bus so the lcd can access the sdram controller simultaneously with activity on the asb. th is means that the arm can read code from rom, or access a peripheral, without being interrupted by video dma. the HMS30C7202 uses a modified ar biter to control mastership on the main asb bus. the arbiter only arbitrates on quad-word boundaries, or when the bus is idle. this is to get the best performance with the arm720t, which uses a quad-word cache line, and also to get the best performance from the sdram, which uses a burst size of eight half-words per access. by arbitrating only when the bus is idle or on quad-word boundaries (a[3:2] = 11), it ensures that cache line fills are not broken up, he nce sdram bursts are not broken up. the sdram controller controls video asb arbitration. this is explained in 6.5 arbitration on page 39. 1.4.2 video bus the video bus connects the lcd controll er with the sdram controller. data transfers are dma controlled. the video bus consists of an address bus, data bus and cont rol signals to/from the sdram controller. the lcd registers are programmed through the fast apb. the sdram controller arbitrates between asb, vga access requests. video always has higher priority than asb access requests. the splitting asb/video bus allows slow asb device accesses sdram with out blocking video dma. 1.4.3 apb HMS30C7202 10 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 10 - there are two apb buses, the fast and slow apb bus. the fast apb bus operates at the speed of the asb, and hosts the usb interface, the so und output interface, the lcd regi sters, etc. these are the high performance peripherals, which are generally dma target s. the slow apb peripherals generally operate at the uart crystal clock frequency of 3.6864mhz, though register access via the apb is at asb speed. the slow apb peripherals do not support dma transfers. this arrangement of running most of the peripherals at a slower clock, and reducing the lo ad on the faster bus, results in sign ificantly reduced power consumption. both apb buses connect to the main asb bus via bridges. the slow apb bridge takes care of all resynchronization, handing over data and control signal s between the asb and uart clock domains in a safe and reliable manner. the fast apb bridge is modified from the normal amba bridge, to allow dma access to fast apb peripherals. additional signals from the dma controller to the apb bridge request select and acknowledge dma transfers to and from dma-aware peripherals. 1.5 sdram controller the sdram controller is a key pa rt of the HMS30C7202 architecture . the sdram controller has two data ports - one for video dma and one for the main asb - and in terfaces to 16-bit wide sdrams. one to four 16, 64, 128, or 256 mbit x16-bit devices are supported, giving a memory size ranging from 2 to 64 mbytes. the main asb and video dma buses are independent, and operate concurrently. the video bus has always higher priority than the main bus. the video interface consists of address, data and control signals. the video access burst size is fixed to 16 words. the address is non-incrementing for words within a burst (as the sdram cont roller only makes use of the first address for each burst request). 1.6 peripheral dma 1.6.1 overview HMS30C7202 incorporates a four-channel, general-purpo se dma controller that operates on the asb. the dma controller is an amba compliant asb bus master with a higher arbitration priority than the arm processor, to ensure low dma latency. since, however, the main asb bus always has lower priority access to the sdram controller than the video bus, it will always get lower priority access to sdram than the lcd. 1.6.2 transfer sizes a device that uses the peripheral dma is the sound output. the sound output data rate is 88.2kb/sec. to ensure reasonable usage of sdram, apb and asb bandwidth, the transfer sizes to the sound controller is a single word. the sdram controller does a complete quad-word access for every sdram access. the maximum sdram bandwidth taken by sound device running concurrently is 0.75%. dma accesses to sound blocks are fully amba compliant, meaning that a word transfer takes two bus cycles. 1.6.3 fly-by the dma controller is tightly coupled to the fast apb bridge . in order for the dma controller to start a transfer, it must first receive a dma data request from one of the peripherals; it will then request mastership of the asb. once granted, the dma controller will retain mastersh ip of the asb until the r equested dma transaction is completed, which ensures correct data in the dma peri pherals (i.e. the arm core cannot modify data while a dma transfer is in progress). the dma transfer request is monitored by the fast apb bridge, which performs the correspondent apb transfer by inverting the read/write line with res pect to the asb and generates a pwrite signal on the apb. the dma transfer is acknowledged on the apb by asse rting a pseldma signal for t he given peripheral. the data is timed by pstb as on a normal apb transfer. the apb address pa is not used for dma transfers. the apb bridge receives two signals from the dma co ntroller called chan [1:0], which tells it which dma channel (peripheral) the dma access is for. all other information comes from monitoring the asb bus signals. for example, the direction of transfer comes from bwrite (the sense is inverted to get the apb signal), and HMS30C7202 11 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 11 - when the sdram transfer completes, comes from the bridge monitoring the bwait asb signal. 1.6.4 timing this is detailed in chapter 9, fast amba peripherals. 1.6.5 sound output in the HMS30C7202, the sound perip heral is connected to the fast apb bus and supported by the dma controller. (note that this is compatible with some operating systems, which require dma-support sound hardware.) 1.7 peripherals universal serial bus (usb) device controller the usb device controller is used to transfer data from/to host system like pc in high-speed (12mbits/s) mode. no external usb transceiver is necessary. ps/2 interface the ps/2 port can be used with keyboard, mice or other ps/ 2 compliant devices. in ps/2 mode the pins are open-drain i/os, as gpios they have normal characteristics. universal asynchronous receiver and transmitter (uart) four uart ports are implemented. one of them supports fu ll modem interface signals. some pins are used as gpio or matrix keyboard pins when not used for uart. irda irda uses uart1 for its sir transfer in 115 kbit/s speed. t he pins are used as gpio or matrix keyboard pins when not used for irda. controller area network (can) the two can ports are used. the pins ar e used as gpio when not used for can. multimedia card (mmc), solid state floppy disk card (ssfdc) mmc or ssfdc memory card can be used as storage device. the pins are used as gpio when not used for mmc or ssfdc. pulse-width-modulated (pwm) interface two pwm output signals are generated. the pins are used as gpio when not used for pwm. matrix keyboard interface matrix keyboard interface supports up to 64 keys. the pins are used as gpio when not used for matrix keyboards. general purpose dma channel one dma channel is provided for exter nal device that needs dma access. the pi ns are used as gpio when not used for dma. dac on chip dac provides 8-bit audio stereo sound. adc a 5 channel adc is implemented for touc h panel, audio input and monitoring of two voltages. no external transistor switch is necessary for touch panel operation. pll cpu, video and usb clocks are generated by three pll with 3.6864 mhz input clock. 1.8 power management the HMS30C7202 incorporates advanced power managem ent functions, allowing the whole device to be put into a standby mode, when only the real time clock r uns. the sdram is put into low-power self-refresh mode to preserve its contents. t he HMS30C7202 may be forced out of this st ate by either a real-time clock wake-up interrupt, a user wake-up event (which would generally be a user pressing the ?on? key) or by the uart ring- indicate input. the power management unit (pmu) contro ls the safe exit from standby mode to operational mode, ensuring that sdram c ontents are preserved. in addi tion, halt and slow modes allow the processor to be halted or run at reduced speed to reduce power cons umption. the processor can be quickly brought out of the halted state by a peripheral interrupt. the advanced power management unit controls all this functionality. in addition, individual devices and peripherals may be powered down when they are not in use. the HMS30C7202 12 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 12 - HMS30C7202 is designed for battery-powered portable applications and incorporates innovative design features in the bus structure and the pmu to r educe power consumption. the slow apb bus allows peripherals to be clocked slowly hence reducing power consumption. the use of three buses reduces the number of nodes that are toggled duri ng a data access, and thereby further reducing power consumption. in addition, clocks to peripherals that are not active can also be gated. 1.8.1 clock gating the high performance peripherals, such as the sdram co ntroller and the lcd controller, run most of the time at high frequencies and careful design, including the use of clock gating, has minimized their power consumption. any peripherals can be power ed down completely when not in use. 1.8.2 pmu the power management unit (pmu) is used to control the overall state the system is in. the system can be in one of five states: run the system is running normally. all clocks are running (e xcept where gated locally), and the sdram controller is performing normal refresh. slow the system operates normally, except the arm is placed in to fast bus mode, and hence is clocked at half its normal rate. idle in this mode, the pmu becomes the bus master until there is an interrupt for the cpu, or the peripheral dma controller requests mastership of the bus. sleep the sdram is placed into self-refresh mode, and internal clocks are gated off. this mode can only be entered from idle mode (that is, the pmu must be asb master before this mode can be entered). the pmu must get bus mastership to ensure that the system is stopped in a safe state and not, for example, halfway through an sdram write. usually this state is only to be entered briefly, on the way to entering deep sleep mode. deep sleep in deep sleep mode, the 3.6864mhz oscillator and the plls are di sabled. this is the lowest power state available. only the 32khz oscillator runs. the r eal time clock and wakeup sections of the pmu are operated from this clock. everything else is powered down, and sdram is in self-refres h mode. this is the normal system ?off? mode. sleep and deep sleep modes are exited either by a user wake-up ev ent (generally pressing the ?on? key), an rtc wake-up alarm, a device reset request, or by a m odem ring indicate event. these interrupt sources go directly to the pmu. in addition, the modem ring indicate signal also goes to the normal interrupt controller to signal an interrupt if there is a ring indicate event in a non-sleep mode. 1.9 test and debug the HMS30C7202 incorporates the arm standard test interf ace controller (tic) allowing 32-bit parallel test vectors to be passed onto the internal bus. this allo ws access to the arm720t macro-cell core, and also to memory mapped devices and peripherals within t he HMS30C7202. in addition, the arm720t includes support for the arm debug architecture (embedded ice), which makes use of a jtag boundary scan port to support debug of code on the embedded processor. the sa me boundary scan port is also used to support a normal pad-ring boundary scan for board level test applications.] HMS30C7202 13 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 13 - 2 pin description 2.1 256-pin diagram 2.1.1 mqfp type lead count body size body thickness lead pitch lead form standoff 256 28.0x28.0 3.37 .40 1.30 .13 note : all dimensions in mm . pin no. pad name pin no. pad name pin no. pad name pin no. pad name 1 ld[4] 65 pmbatok 129 rd[20] 193 uvddo6 2 ld[3] 66 npllenable 130 uvddo2 194 sa[7] 3 ld[2] 67 ntest 131 rd[19] 195 sa[8] 4 ld[1] 68 nuring 132 rd[18] 196 sa[9] 5 ld[0] 69 nudtr 133 rd[17] 197 sa[10] 6 kscano[1] 70 nucts 134 rd[16] 198 sa[11] 7 kscano[2] 71 nurts 135 rd[15] 199 sa[12] fi g ure t clear in the watchdo g timer mode with manual reset pin location and si g nal HMS30C7202 top view ld[4] ld[3] ld[2] ld[1] ld[0] kscano[1] kscano[2] kscano[0] kscano[3] kscano[4] kscano[5] kscano[6] kscano[7] kscani[0] kscani[1] kscani[2] kscani[3] kscani[4] kscani[5] kscani[6] kscani[7] tdi tck tms ntrst tdo rtcoscin rtcoscout oscin oscout uvssi[0] testscan uvddi[0] uusbvdd ausbp ausbn uusbvss upllvdd[1] pllfilt[1] upllvss[1] pllfilt[2] upllvdd[0] pllfilt[0] upllvss[0] udacvdd adacr adacl udacvss uavddadc avrefadc adin[0] adin[1] adin[2] adin[3] adin[4] uavssadc atsxp atsxn atsyp atsyn npmwakeup npor nreset pmadapok pmbatok npllenable ntest nuring nudtr nucts nurts nudsr nudcd usin[0] usout[0] usin[1] usout[1] cantx[0] canrx[0] portb[6] portb[7] portb[8] portb[9] portb[10] portb[11] timerout psdat uvsso[0] psclk uvddo[0] pwm[0] pwm[1] cantx[1] canrx[1] uvssi[1] mmccmd uvddi[1] mmcdat nmmccd mmcclk ndmareq ndmaack nrcs[3] nrcs[2] nrcs[1] nrcs[0] bootbit[1] bootbit[0] nroe exprdy nrwe[3] nrwe[2] uvsso[1] nrwe[1] uvddo[1] nrwe[0] rd[31] rd[30] rd[29] rd[28] rd[27] rd[26] rd[25] rd[24] rd[23] rd[22] uvsso[2] rd[21] rd[20] uvddo[2] rd[19] rd[18] rd[17] rd[16] rd[15] rd[14] rd[13] rd[12] rd[11] rd[10] rd[9] rd[8] rd[7] uvsso[3] rd[6] uvddo[3] rd[5] rd[4] rd[3] rd[2] rd[1] rd[0] ra[0] ra[1] ra[2] ra[3] ra[4] ra[5] uvddi[2] scan_en uvssi[2] ra[6] ra[7] uvsso[4] ra[8] uvddo[4] ra[9] ra[10] ra[11] ra[12] ra[13] ra[14] ra[15] ra[16] ra[17] ra[18] ra[19] ra[20] ra[21] ra[22] uvsso[5] ra[23] uvddo[5] ra[24] sa[3] sa[4] sa[2] sa[5] sa[1] sa[6] uvsso[6] sa[0] uvddo[6] sa[7] sa[8] sa[9] sa[10] sa[11] sa[12] sa[13] uvsso[7] sa[14] uvddo[7] nscs[1] nscs[0] nsras nscas nswe scke[1] scke[0] sclk sdqmu uvsso[8] sdqml uvddo[8] sd[8] sd[7] sd[9] sd[6] sd[10] sd[5] sd[11] uvsso[9] sd[4] uvddo[9] sd[12] uvddi[3] sd[3] uvssi[3] sd[13] sd[2] sd[14] sd[1] sd[15] sd[0] uvsso[10] llp uvddo[10] lac lblen lcp lfp lcden ld[15] ld[14] ld[13] ld[12] ld[11] ld[10] ld[9] ld[8] ld[7] ld[6] uvsso[11] ld[5] uvddo[11] ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 HMS30C7202 14 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 14 - 8 kscano[0] 72 nudsr 136 rd[14] 200 sa[13] 9 kscano[3] 73 nudcd 137 rd[13] 201 uvsso7 10 kscano[4] 74 usin[0] 138 rd[12] 202 sa[14] 11 kscano[5] 75 usout[0] 139 rd[11] 203 uvddo7 12 kscano[6] 76 usin[1] 140 rd[10] 204 nscs[1] 13 kscano[7] 77 usout[1] 141 rd[9] 205 nscs[0] 14 kscani[0] 78 cantx[0] 142 rd[8] 206 nsras 15 kscani[1] 79 canrx[0] 143 rd[7] 207 nscas 16 kscani[2] 80 portb[6] 144 uvsso3 208 nswe 17 kscani[3] 81 portb[7] 145 rd[6] 209 scke[1] 18 kscani[4] 82 portb[8] 146 uvddo3 210 scke[0] 19 kscani[5] 83 portb[9] 147 rd[5] 211 sclk 20 kscani[6] 84 portb[10] 148 rd[4] 212 sdqmu 21 kscani[7] 85 portb[11] 149 rd[3] 213 uvsso8 22 tdi 86 timerout 150 rd[2] 214 sdqml 23 tck 87 psdat 151 rd[1] 215 uvddo8 24 tms 88 uvsso0 152 rd[0] 216 sd[8] 25 ntrst 89 psclk 153 ra[0] 217 sd[7] 26 tdo 90 uvddo0 154 ra[1] 218 sd[9] 27 rtcoscin 91 pwm[0] 155 ra[2] 219 sd[6] 28 rtcoscout 92 pwm[1] 156 ra[3] 220 sd[10] 29 oscin 93 cantx[1] 157 ra[4] 221 sd[5] 30 oscout 94 canrx[1] 158 ra[5] 222 sd[11] 31 uvssi0 95 uvssi1 159 uvddi2 223 uvsso9 32 testscan 96 mmccmd 160 scan_en 224 sd[4] 33 uvddi0 97 uvddi1 161 uvssi2 225 uvddo9 34 avddusb 98 mmcdat 162 ra[6] 226 sd[12] 35 ausbp 99 nmmccd 163 ra[7] 227 uvddi3 36 ausbn 100 mmcclk 164 uvsso4 228 sd[3] 37 avssusb 101 ndmareq 165 ra[8] 229 uvssi3 38 pllvdd[1] 102 ndmaack 166 uvddo4 230 sd[13] 39 pllfilt[1] 103 nrcs[3] 167 ra[9] 231 sd[2] 40 pllvss[1] 104 nrcs[2] 168 ra[10] 232 sd[14] 41 pllfilt[2] 105 nrcs[1] 169 ra[11] 233 sd[1] 42 pllvdd[0] 106 nrcs[0] 170 ra[12] 234 sd[15] 43 pllfilt[0] 107 bootbit[1] 171 ra[13] 235 sd[0] 44 pllvss[0] 108 bootbit[0] 172 ra[14] 236 uvsso10 45 avdddac 109 nroe 173 ra[15] 237 llp 46 adacr 110 exprdy 174 ra[16] 238 uvddo10 47 adacl 111 nrwe[3] 175 ra[17] 239 lac 48 avssdac 112 nrwe[2] 176 ra[18] 240 lblen 49 avddadc 113 uvsso1 177 ra[19] 241 lcp 50 avrefadc 114 nrwe[1] 178 ra[20] 242 lfp 51 adin[0] 115 uvddo1 179 ra[21] 243 lcden 52 adin[1] 116 nrwe[0] 180 ra[22] 244 ld[15] 53 adin[2] 117 rd[31] 181 uvsso5 245 ld[14] 54 adin[3] 118 rd[30] 182 ra[23] 246 ld[13] 55 adin[4] 119 rd[29] 183 uvddo5 247 ld[12] 56 avssadc 120 rd[28] 184 ra[24] 248 ld[11] 57 atsxp 121 rd[27] 185 sa[3] 249 ld[10] 58 atsxn 122 rd[26] 186 sa[4] 250 ld[9] 59 atsyp 123 rd[25] 187 sa[2] 251 ld[8] 60 atsyn 124 rd[24] 188 sa[5] 252 ld[7] 61 npmwakeup 125 rd[23] 189 sa[1] 253 ld[6] 62 npor 126 rd[22] 190 sa[6] 254 uvsso11 63 nreset 127 uvsso2 191 uvsso6 255 ld[5] 64 pmadapok 128 rd[21] 192 sa[0] 256 uvddo11 HMS30C7202 15 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 15 - 2.1.2 fbga type HMS30C7202 16 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 16 - f2 kscani[1] r6 canrx[0] l15 rd[7] b11 nscas g6 kscani[2] l7 portb[6] k11 uvsso3 f10 nswe g5 kscani[3] m7 portb[7] k12 rd[6] e10 scke[1] g4 kscani[4] n7 portb[8] k13 uvddo3 d10 scke[0] g1 kscani[5] t7 portb[9] k16 rd[5] a10 sclk g3 kscani[6] p7 portb[10] k14 rd[4] c10 sdqmu g2 kscani[7] r7 portb[11] k15 rd[3] b10 uvsso8 h7 tdi k8 timerout j10 rd[2] g9 sdqml h6 tck l8 psdat j11 rd[1] f9 uvddo8 h5 tms m8 uvsso0 j12 rd[0] e9 sd[8] h4 ntrst n8 psclk j13 ra[0] d9 sd[7] h1 tdo t8 uvddo0 j16 ra[1] a9 sd[9] h3 rtcoscin p8 pwm[0] j14 ra[2] c9 sd[6] h2 rtcoscout r8 pwm[1] j15 ra[3] b9 sd[10] j7 oscin k9 cantx[1] h10 ra[4] g8 sd[5] j6 oscout l9 canrx[1] h11 ra[5] f8 sd[11] j5 uvssi0 m9 uvssi1 h12 uvddi2 e8 uvsso9 j4 testscan n9 mmccmd h13 scan_en d8 sd[4] j2 uvddi0 r9 uvddi1 h15 uvssi2 b8 uvddo9 j3 avddusb p9 mmcdat h14 ra[6] c8 sd[12] j1 ausbp t9 nmmccd h16 ra[7] a8 uvddi3 j8 ausbn j9 mmcclk h9 uvsso4 h8 sd[3] k5 avssusb m10 ndmareq g12 ra[8] e7 uvssi3 k4 pllvdd[1] n10 ndmaack g13 uvddo4 d7 sd[13] k2 pllfilt[1] r10 nrcs[3] g15 ra[9] b7 sd[2] k3 pllvss[1] p10 nrcs[2] g14 ra[10] c7 sd[14] k6 pllfilt[2] l10 nrcs[1] g11 ra[11] f7 sd[1] k7 pllvdd[0] k10 nrcs[0] g10 ra[12] g7 sd[15] k1 pllfilt[0] t10 bootbit[1] g16 ra[13] a7 sd[0] l6 pllvss[0] l11 bootbit[0] f11 ra[14] f6 uvsso10 l2 avdddac r11 nroe f15 ra[15] b6 llp l4 adacr n11 exprdy f13 ra[16] d6 uvddo10 l3 adacl p11 nrwe[3] f14 ra[17] c6 lac l5 avssdac m11 nrwe[2] f12 ra[18] e6 lblen l1 avddadc t11 uvsso1 f16 ra[19] a6 lcp m4 avrefadc n12 nrwe[1] e13 ra[20] d5 lfp m2 adin[0] r12 uvddo1 e15 ra[21] b5 lcden m5 adin[1] m12 nrwe[0] e12 ra[22] e5 ld[15] m3 adin[2] p12 rd[31] e14 uvsso5 c5 ld[14] m1 adin[3] t12 rd[30] e16 ra[23] a5 ld[13] n4 adin[4] n13 rd[29] d13 uvddo5 d4 ld[12] n2 avssadc r13 rd[28] d15 ra[24] b4 ld[11] n3 atsxp p13 rd[27] d14 sa[3] c4 ld[10] n1 atsxn t13 rd[26] d16 sa[4] a4 ld[9] p2 atsyp r14 rd[25] c15 sa[2] b3 ld[8] p1 atsyn t14 rd[24] c16 sa[5] a3 ld[7] p3 npmwakeup p14 rd[23] c14 sa[1] c3 ld[6] r1 npor t15 rd[22] b16 sa[6] a2 uvsso11 r2 nreset r15 uvsso2 b15 uvsso6 b2 ld[5] t1 pmadapok t16 rd[21] a16 sa[0] a1 uvddo11 HMS30C7202 17 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 17 - 2.2 pin descriptions table 2-2 describes the function of all t he external signals to the HMS30C7202. type description type description o output oa analog output i input ia analog input io input/output ioa analog input/output is input with schmitt level input threshold p power input u suffix to indicate integral pull-up d suffix to indicate integral pull-down m suffix to multiple function pin table 2-1 pin signal type definition 2.2.1 external signal functions function signal name signal type description ld[15:0] om lcd data bus. allow 5:6:5 tft, color (using [7:0]) or mono, using [3:0] or [7:0] lcp o lcd clock pulse llp o lcd line pulse (hsync for tft) lfp o lcd frame pulse (vsync for tft) lac o lcd ac bias (clock enable for tft) lcden o display enable signal for lcd. enables high voltage to lcd lcd lblen om lcd backlight enable ra[24:0] o rom address bus rd[31:0] iom rom data bus nrcs[3:0] om rom chip select outputs nroe o rom output enable signal nrwe[3:0] om rom write enable signals exprdy i wait from external i/o static memory interface bootbit[1:0] i 8/16/32 bit rom selection sclk o sdram clock output scke[1:0] o sdram clock enable output nsras o sdram ras output nscas o sdram cas output nswe o sdram write enable output nscs[1:0] o sdram chip select outputs sdqml o sdram lower data byte enable sdqmu o sdram upper data byte enable sd[15:0] io sdram data bus sdram interface sa[14:0] o sdram address bus ndmareq im dma request input (active low) dma interface ndmaack om dma acknowledge output nudcd0 im uart data carrier detect input nudsr0 im uart data set ready input nucts0 im uart clear to send input usin[3:0] im uart serial data inputs usout[3:0] om uart serial data outputs nudtr0 om uart data terminal ready nurts0 om uart request to send uart nuring0 im uart ring input si gnal (wake-up signal to pmu) irdin1 im irda infra-red data input irda irdout1 om irda infra-red data output ausbp aio usb positive signal usb ausbn aio usb negative signal HMS30C7202 18 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 18 - function signal name signal type description avddusb p usb analog vdd avssusb p usb analog vss pwm[1:0] om pulse width modulation output pwm timerout om timer output cantx[1:0] om controlled area network data output can canrx[1:0] im controlled area network data input kscano[7:0] om matrix keyboard scan outputs matrix keyboard kscani[7:0] im matrix keyboard scan inputs ps2d odm ps2 data signal ps/2 interface ps2ck odm ps2 clock signal ssdo om mmc card controller data output ssdi im mmc card controller data input ssclk om mmc card controller clock output mmc nsscs om mmc card controller chip select smd[7:0] iom smart media card (ssfdc) data signals nsmwp om smart media card (ssfdc) write protect nsmwe om smart media card (ssfdc) write enable smale om smart media card (ssfdc) address latch enable smcle om smart media card (ssfdc) command latch enable nsmcd im smart media card (ssfdc) card detection signal nsmce om smart media card (ssfdc) chip enable nsmre om smart media card (ssfdc) read enable ssfdc (smartcard) nsmrb im smart media card (ssfdc) ready/nbusy signal atsxp io touch screen switch x high drive atsxn o touch screen switch x low drive atsyp io touch screen switch y high drive atsyn o touch screen switch y low drive adin[4:0] ai adc inputs for mic, battery, touch avddadc p adc analog vdd avssadc p adc analog vss adc avrefadc ai adc reference voltage avdddac p dac analog vdd avssdac p dac analog vss adacr ao sound dac output (right channel) dac adacl ao sound dac output (left channel) pllvdd[1:0] p pll analog vdd pllvss[1:0] p pll analog vss pll pllfilt[2:0] ai external pll loop filter input pins (1 per pll) porta[15:0] iom general purpose input/output signals portb[11:0] iom general purpose input/output signals portc[10:0] iom general purpose input/output signals portd[8:0] iom general purpose input/output signals gpio porte[24:0] iom general purpose input/output signals npor is power on reset input. schmitt level input with pullup npmwakeup is wake-up ?on-key? input. low causes pmu to exit standby state. nreset io reset input (also driven out in por, until the pll is locked) pmadapok i adapter power ok system pmbatok i main battery ok rtcoscin i rtc oscillator input rtcoscout o rtc oscillator output oscin i main oscillator input oscillator oscout o main oscillator output vddcore[3:0] p core vdd supply (2.5v) digital power/ vsscore[3:0] p core vss supply HMS30C7202 19 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 19 - function signal name signal type description vdd[11:0] p io vdd supply (3.3v) ground vss[11:0] p io vss supply tck iu jtag boundary scan and debug test clock ntrst id jtag boundary scan and debug test reset tms iu jtag boundary scan and debug test mode select tdi iu jtag boundary scan and debug test data input jtag tdo o jtag boundary scan and debug test data output test npllenable id low to enable pll. high to bypass pll with clock from oscin testscan id scan test mode enable scan_en id scan chain activated ntest iu test mode select table 2-2 external signal functions HMS30C7202 20 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 20 - 2.2.2 multiple function pins 2.2.2.1 port a data input/output primary (ntest | npllenable) & ~aen* & ~amulsel** gpio enable (ntest | npllenable ) & aen & ~amulsel multifunction enable (ntest | npllenable ) & ~aen & amulsel both enable (ntest | npllenable ) & aen & amulsel analog test (~ntest & ~npllenable) i o i o i o i o i o kscano0 porta0 porta0 porta0 porta0 porta0 tpll3freqsel[0] kscano1 porta1 porta1 porta1 porta1 porta1 tpll3freqsel[1] kscano2 porta2 porta2 porta2 porta2 porta2 tpll3freqsel[2] kscano3 porta3 porta3 porta3 porta3 tpll3freqsel[3] kscano4 porta4 porta4 porta4 porta4 tpll3freqsel[4] kscano5 porta5 porta5 usin2 porta5 porta5 tpll3freqsel[5] kscano6 porta6 porta6 usout2 porta6 porta6 tpll3pwdn kscano7 porta7 porta7 irdout porta7 porta7 tpll3clkout kscani0 porta8 porta8 porta8 porta8 porta8 tpll3clkqout kscani1 porta9 porta9 porta9 porta9 porta9 tpll3lockout kscani2 porta10 porta10 porta10 porta10 porta10 taiostop kscani3 porta11 porta11 porta11 porta11 tach[0] kscani4 porta12 porta12 porta12 porta12 tach[1] kscani5 porta13 porta13 usin3 porta13 porta13 tach[2] kscani6 porta14 porta14 usout3 porta14 porta14 tach[3] kscani7 porta15 porta15 irdin porta15 porta15 tach[4] * aen : gpio port a enable register (0x8002.301c). ** amulsel : gpio port a multi-func tion select register (0x8002.30a4). 2.2.2.2 port b data input/output primary ntest & ~npllenable & ~ben* gpio enable ntest & ~npllenable & ben normal bypass ntest & npllenable normal test ~ntest & npllenable & ~ben uart test ~ntest & npllenable & ben analog test ~ntest & ~npllenable i o i o i o i o i o i o nuring portb0 portb0 nuring tblclk nuring nudtr portb1 portb1 nudtr tbcclk nudtr nucts portb2 portb2 nucts nucts taclk nurts portb3 portb3 nurts nurts tad[9] nudsr portb4 portb4 nudsr nudsr tad[8] nudcd portb5 portb5 nudcd nudcd tad[7] portb6 portb6 portb6 portb6 tbfclk tbfclk portb7 portb7 portb7 portb7 tbqfclk tbqfclk portb8 portb8 portb8 portb8 tbbclk tbbclk portb9 portb9 portb9 portb9 tack tack tack portb10 portb10 portb10 portb10 tblclk treqb treqb treqb portb11 portb11 portb11 portb11 tbcclk treqa treqa treqa * ben : gpio port b enable register (0x8002.303c). HMS30C7202 21 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 21 - 2.2.2.3 port c data input/output primary (ntest | npllenable) & ~cen* gpio enable (ntest | npllenable) & cen analog test ~ntest & ~npllenable i o i o i o timerout portc0 portc0 tad[2] cantx0 portc1 portc1 tad[4] canrx0 portc2 portc2 tad[3] psdat psdat portc3 portc3 tad[1] psclk psclk portc4 portc4 tad[0] pwm0 portc5 portc5 tdiostop pwm1 portc6 portc6 tdleft ndmareq portc7 portc7 tdd[2] ndmaack portc8 portc8 tdd[1] nrcs2 / [nrcs2dma] portc9 portc9 nrcs3 portc10 portc10 tdd[0] * cen : gpio port c enable register (0x8002.305c). 2.2.2.4 port d data input/output primary (ntest | npllenable ) & ~den* gpio enable (ntest | npllenable ) & den analog test ~ntest & ~npllenable i o i o i o ld8 portd0 portd0 tpll1pwdn ld9 portd1 portd1 tpll1freqsel[0] ld10 portd2 portd2 tpll1freqsel[1] ld11 portd3 portd3 tpll1freqsel[2] ld12 portd4 portd4 tpll1freqsel[3] ld13 portd5 portd5 tpll1freqsel[4] ld14 portd6 portd6 tpll1freqsel[5] ld15 portd7 portd7 tpll1pclkin lblen portd8 portd8 z den : gpio port d enable register (0x8002.307c). HMS30C7202 22 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 22 - 2.2.2.5 port e data input/output primary (ntest & ~halfwordsel & ~een* 1 ) gpio enable (ntest & een) multifunction 1 (ntest & halfwordsel* 3 & ~een & ~swap* 2 ) multifunction 2 (ntest & halfwordsel & ~een & swap) test mode (~ntest) analog test (~ntest & ~npllenable) i o i o i o i o i o i o rd16 rd16 porte0 porte0 nusboe smd7 smd7 rd16 rd16 rd17 rd17 porte1 porte1 uvpo smd6 smd6 rd17 rd17 rd18 rd18 porte2 porte2 uvmo smd5 smd5 rd18 rd18 rd19 rd19 porte3 porte3 ususpend smd4 smd4 rd19 rd19 rd20 rd20 porte4 porte4 urcvin smd3 smd3 rd20 rd20 rd21 rd21 porte5 porte5 uvm smd2 smd2 rd21 rd21 rd22 rd22 porte6 porte6 uvp smd1 smd1 rd22 rd22 rd23 rd23 porte7 porte7 smd7 smd7 smd0 smd0 rd23 rd23 rd24 rd24 porte8 porte8 smd6 smd6 nsmwp rd24 rd24 rd25 rd25 porte9 porte9 smd5 smd5 nsmwe rd25 rd25 rd26 rd26 porte10 porte10 smd4 smd4 smale rd26 rd26 rd27 rd27 porte11 porte11 smd3 smd3 nsmre rd27 rd27 rd28 rd28 porte12 porte12 smd2 smd2 nsmce rd28 rd28 rd29 rd29 porte13 porte13 smd1 smd1 nsmcd rd29 rd29 rd30 rd30 porte14 porte14 smd0 smd0 smcle rd30 rd30 rd31 rd31 porte15 porte15 nsmwp nsmrb rd31 rd31 nrw2 porte16 porte16 nsmwe canrx1 porte16 nrw3 porte17 porte17 smale cantx1 porte17 mmccmd / ssdi mmccmd/ zero porte18 porte18 nsmre nusboe porte18 tdd[6] mmcdat mmcdat / ssdo porte19 porte19 nsmce uvpo porte19 tdd[5] nmmccd zero/ nsscs porte20 porte20 nsmcd uvmo porte20 tdd[4] mmcclk / ssclk porte21 porte21 smcle ususpend porte21 tdd[3] canrx1 porte22 porte22 nsmrb urcvin porte22 tdd[7] cantx1 porte23 porte23 porte23 uvm porte23 tdright ra24 porte24 porte24 ra24 uvp ra24 * 1 een : gpio port e enable register (0x8002.309c). * 2 swap : swap pin configuration register (0x8002.30a8). * 3 when halfwordsel is enable, multifunction 1 or 2 is usabl e instead of primary rd16~31. to enable halfwordsel , you should set bottom bits[1:0] of smi registers(memc fg0~3 on the table 7-1) to [01 or 10 or 11]. note : a 32 bit access is not possible without rd16~rd31. so user should make program to disable porte for 32bit access time. we are not guarantee that the program is alternated 32bit access(rd0~31) with porte. HMS30C7202 23 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 23 - 2.2.2.6 usb transceiver test & analog test data input/output ntest & ~ntest & primary ~lcden & ~usbtranssel ~lcden & usbtranssel i o i o i o ld0 tcanck tnusboe ld1 tcansm tuvpo ld2 tcansi tuvmo ld3 tcanso tususpend ld4 turcvin ld5 tuvm ld6 tuvp figure usb transceiver test scheme ver1.5 2.2.2.7 dma data input/output ntest & ndmaack ~ndmaack i o i o nroe nroedma nrwe0 nrwe0dma 2.2.2.8 inverter chain when ntestana == 0, bootbit1 ? nrwe1 (total 50ns delay expected) HMS30C7202 24 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 24 - 3 arm720t macrocell 3.1 arm720t macrocell for details of the arm720t, please refer to the arm720t data sheet (ddi 0087). HMS30C7202 25 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 25 - 4 memory map there are five main memory map divisions, outlined in table 4-1 top-level address map base address (byte) base address (hex) size description 0 mbyte 64 mbytes 128 mbytes 192 mbytes 256 mbytes 0x0000.0000 0x0400.0000 0x0800.0000 0x0c00.0000 0x1000.0000 32mbytes 32mbytes 32mbytes 32mbytes 256mbytes rom chip select 0 rom chip select 1 rom chip select 2 rom chip select 3 reserved 512 mbytes 0x2000.0000 512mbytes reserved 1024 mbytes 1056 mbytes 1088 mbytes 1120 mbytes 1152 mbytes 0x4000.0000 0x4200.0000 0x4400.0000 0x4600.0000 0x4800.0000 32mbytes 32mbytes 896mbytes sdram chip select 0 sdram chip select 1 sdram mode register chip 0 sdram mode register chip 1 reserved 2048 mbytes 0x8000.0000 336kbytes peripherals table 4-1 top-level address map the rom has an address space of 256mbytes that is sp lit equally between four external rom chip select. actual address range for each chip select is 32mbytes with 25 external address signals. there is a maximum of 64mbytes of sdram space. reading from the address space(over 0x4400.0000) above the sdram address space(0x4000.0000~0x43ff. ffff) sets the m ode registers in the sdram (to set the sdram mode register, read operation from the range s of sdram mode register is needed. for more information, refer 6.3. ). the peripheral address space is subdivided into thr ee main areas: those on the asb, the fast apb and the slow apb. the base address for the peripherals is given in table 3-2: peripherals base addresses. function base address (hex) name description 0x7f00.0000 intsram base internal sram 0x7f00.0800 reserved ~0x7fff.ffff 0x8000.0000 sdramc base sdram controller 0x8000.1000 pmu base pmu/pll 0x8000.2000 reserved 0x8000.3000 busc base bus controller 0x8000.4000 dmac base dmac asb peripherals 0x8000.5000 reserved ~0x8000.ffff 0x8001.0000 lcd lcd 0x8001.1000 reserved 0x8001.2000 usb base usb 0x8001.3000 sound base sound 0x8001.4000 reserved 0x8001.5000 mmc base mmc/ spi 0x8001.6000 smc base smc fast apb peripherals 0x8001.7000 reserved ~0x8001.ffff 0x8002.0000 u0 base uart 0 0x8002.1000 u1 base uart 1 (support sir) 0x8002.2000 kbd base kbd 0x8002.3000 gpio base gpio 0x8002.4000 intc base intc 0x8002.5000 timer base timer 0x8002.6000 reserved ~0x8002.7fff 0x8002.8000 rtc base rtc 0x8002.9000 adc base adc 0x8002.a000 reserved slow apb peripherals 0x8002.b000 wdt base wdt HMS30C7202 26 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 26 - function base address (hex) name description 0x8002.c000 ps2 base ps2 0x8002.d000 u2 base uart2 0x8002.e000 u3 base uart3 0x8002.f000 can0 base can0 0x8003.0000 can1 base can1 0x8003.1000 reserved ~0x8004.ffff table 4-2 peripherals base addresses HMS30C7202 27 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 27 - 5 pmu & pll the HMS30C7202 is designed primarily for hpc and ot her portable computing appl ications. therefore there are 4 operating modes to reduce powe r consumption and extend battery life. z run - normal operation (used for cpu-intensive tasks) z slow - half-speed operation used when the applicati on interacts with a user (e.g. word processing) z idle - where the cpu operation is halted but peripherals operation continue (such as scr een refresh, or serial communications) z sleep & deep sleep - this mode will be perceived as `off ' by the user, but the sdram contents is maintained and only the real-time clock is running. the transition between these modes is controlled by the pmu (see also 7.3 power management states, page 7-5). the pmu is an asb slave unit to allow the cpu to wr ite to its control register s, and is an asb master unit to provide the mechanism for stopping the arm core's internal clock. 5.1 block functions clock generator the clock generator module controls the plls and gating clocks while the pll outputs are unknow and to ensure that clocks are available during test modes and during reset sequences. fclk (arm processor and sdram controller clock) derived from pll3, programmable between 49.7664 mh z and 82.944 mhz by a 6-bit register (default frequency is 70.0416 mhz). there are two methods for updating frequency, depending upon the state of bit 6 of the clock control register clkctl (see clkctl register on page 7-11). if bit 6 is set, t hen any data written to bits [5:0] of the clkctl register are immediately transferred to the pins of pll3, thus causing the loop to unlock and to mute fclk. this is only a safe mode of operation if pll3 frequency and ma rk-space ratio is guaranteed to be within limits immediately after the lock detect signal has become ac tive. if bit 6 is not set, then the HMS30C7202 must enter deep sleep mode before bits [5:0] of t he clock control register are transferred to pll3. to switch between the two frequencies when bit 6 is not set: z software writes the new va lue into the clkctl register z set a real time clock alarm to wake the HMS30C7202 in 2 seconds z enter deep sleep mode by writing to the pmumode register z the HMS30C7202 will power up with pll3 running at the new frequency bclk bus clock is generated by the pmu by dividing fclk by 2. vclk vclk is generated by pll1 and clocks the lcd contro ller. the frequency is selectable between 24.8832mhz or 41.472mhz (default is 30.4128 mhz). the vclk pll is disabled when on bnres is active or when the pmu is put into deep sleep mode. on exit from ei ther of these conditions, the vclk pll must be re- enabled by software. changing frequency: 1. software must first disable the vclk pll, by writ ing a `0' to the pll1enable bit of the clkctl register. 2. write the new value to the pll1freq bit. 3. re-enable the vclk pll by writing 1 to the pll1enable bit. cclk cclk is generated by pll2 and clocks the can and the usb block - nominally 48mhz. the cclk pll is disabled when bnres active or when the pmu is put in to deep sleep mode. on exit from either of these conditions, the cclk pll must be re-enabled by software. pmu state machine the state machine handles the transition between t he power management states described below. the cpu HMS30C7202 28 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 28 - can write to the pmu mode registers (which is what would typically ha ppens when a user switches off the device) and the state machine will pr oceed to the commanded state. 5.2 power management 5.2.1 state diagram figure 5-1 pmu power management state diagram 5.2.2 power management states run the system is running normally. all clocks running (e xcept where gated locally). the sdram controller is performing normal refresh. HMS30C7202 29 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 29 - slow the cpu is switched into fastbus mode, and hence runs at the bclk rate (half the fclk rate). this is the default mode after exiting sleep mode. idle in this mode, the pmu becomes the bus master until there is either a fast or normal interrupt for the cpu, or the peripheral dma controller reques ts master-ship of the bus. this will cause the clocks in the cpu to stop when it attempts an asb access. this mode can be initiated by writing the pmu_idle value to the pmu mode regist er (in run or slow mode), or by a wakeup signal while the cpu is in sleep or deep sleep mode. sleep in this mode, the sdram is put into self-refresh mode, and internal cl ocks are gated off. this mode can only be entered from idle mode (the pmu bus master must have mastership of the asb before this mode can be entered). the pmu must be bus master to ensure that the syst em is stopped in a safe state, and is not half way through a sdram write (for example). both the video and communication clocks should be disabled before entering this state. usually this state would only be entered briefly, on the way to entering deep sleep mode. deep sleep in deep sleep mode, the 3.6864mhz oscillator and the pll are disabled. this is the lowest power state available. only the 32 khz oscillator runs, driving the r eal time clock and the pmu. clocked circuitry in the pmu runs at 4khz (i.e. the rtc clock divided by 8). everything else is powered down, and sdram is in self refresh mode. this is the normal system "off" mode. sleep and deep sleep modes are exited either by a us er wake-up event (generally pressing the "on" key), or by an rtc wake-up alarm, or by a modem ring indi cate event. these interrupt sources go directly to the pmu. 5.2.3 wake-up debounce and interrupt the wake-up events are debounced as follows: each of the event signals which are liable to noise (nreset, rtc, npmwakeup, and modem ring indicator, power adapter condition) is re-timed to a 250 hz clock der ived from the low power (4 khz) clock. after filtering to a quarter of 250 hz, each event has an associated `s ticky' register bit. npmwakeup is an external input, which may be typically connected to an "on" key. a `sticky' bit is a register bit that is set by the inco ming event, but is only reset by the cpu. thus should a pll drop out of lock momentarily (for example) the cpu will be informed of the event, even if the pll has regained lock by the time the cpu can read its associated register bit. the npmwakeup, modem, real time clock , hotsync(gpiob[10]) and power adapter condition inputs are combined to form the pmu interrupt. each of these four interrupt sources can wake up from deep- sleep mode individually and all wake-up operation can not mask able. but when wake-up occur, user can mask interrupt signal to inform interrupt controller. to make use of the npmwakeup interrupt, (for exampl e) controlling software will need to complete the following tasks: z enable the npmwakeup interrupt bit, by writing 1 to bit[11] of the reset / st atus register (pmustat register). z once an interrupt has occurred, read t he reset / status register to identify the source(s) of interrupt. in the case of a npmwakeup event, the register will return 0x10. z clear the appropriate `sticky' bit by writing a 1 to the appropriate location (in the npmwakeup case, this will be 0x10.). but even though the npmwakeup interrupt mask bit is mask ed, by writing 0 to bit[11] of the reset status register, chip shall wake-up with npmwakeup signal. portb[10] (hotsync) wake-up sequence the hotsync interrupt is or gated with npmwakeup to support additional wake up sources. hotsync input signal can be used as a wake up source; they are enabled using the interrupt mask register. after wake up, s/w should program the portb interrupt mask register and/or the pmu resetstatus register. HMS30C7202 30 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 30 - one other possible application is to use the ndcd signal, from the uart interface, as a wake up source, by connecting ndcd to a portb input. in deep sleep mo de, ndcd can wake up the system by generating a portb interrupt request to the pmu block. the pm u state machine then returns the system to the operational mode. 5.3 registers address name width default description 0x8000.1000 pmumode 4 pmu mode register 0x8000.1010 pmuid 32 pmu id register 0x8000.1020 pmustat 17 pmu reset/pll status register 0x8000.1028 pmuclk 16 0x1b pmu clock control register 0x8000.1030 pmudbct 9 pmu debounce test register 0x8000.1038 pumplltr 21 pmu pll test register table 5-1 pmu register summary 5.3.1 pmu mode register (pmumode) this read/write register is to change from run mode or slow mode into a different mode. the encoding is shown below, in pmu mode encoding. the register can only be accessed in run mode or slow mode (these are the only modes in which the processor is active). therefore, the processor will nev er be able to read values for modes other than mode 0x00 and mode 0x 01. a test controller may read other values as l ong as clocks are enabled with bit 8 of the pmu debounce counter test register. for more information, please refer 5.3.6. 0x80001000 31 ? 3 2 1 0 wakeup mode sel bits type function 31:4 - reserved 3 r/w writing a `1' to this bit allows pmu to exit deep sleep mode when pins pmbatok and pmadapok are both low. writing a `0' to this bit prevents the pmu from leaving deep sleep mode when pmbatok and pmadapok are both low 2:0 r/w value pmu mode encoding 0x04 initialization mode 0x01 run mode 0x00 slow mode 0x02 idle mode 0x03 sleep mode 0x07 deep sleep mode note: all other values in the above table are undefined. 5.3.2 pmu id register (pmuid) this read-only register returns a unique chip revisi on id. revision 0 of the HMS30C7202 device (the first revision) will return the constant value 0x00720200. 0x80001010 31 ? 0 0x00720200 5.3.3 pmu reset /pll status register (pmustat) this read/write register provides status information on power on reset and the pll status. the allocation is a shown in following two tables: resetstatus register bits. the bits in this register are `sticky' bits. for a definition of a sticky bit, please refer to 5.2.3 wake- up debounce and interrupt. generally, this register will be HMS30C7202 31 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 31 - read each time the arm exits reset mode, so that the ar m can identify what event has caused it to exit from reset mode. 0x80001020 16 warm reset 15 14 13 12 11 10 9 8 hotsync intr adaptor intr rtc intr mring intr wakeup intr hotsync status wdt rst warm rst status 7 6 5 4 3 2 1 0 adaptor status rtc status mring status wakeup status pll3 lock pll2 lock pll1 lock por status bits type function 31:17 - r e s e r v e d 16 w warm reset. writing a `1' causes nreset to be asserted. writing `0' has no effect. 15 r/w hotsync interrupt mask. when reads, 0 = disable hotsync interrupt from external pin. 1 = enable hotsync interrupt from external pin. 14 r/w no external power interrupt mask. when reads, 0 = disable pmu interrupt from pmadapok low. 1 = enable pmu interrupt from pmadapok low. 13 r/w rtcevt interrupt mask. when reads, 0 = disable pmu interrupt from rtc 1 = enable pmu interrupt from rtc 12 r/w rievt interrupt mask pmu interrupt request / clear when reads, 0 = disable pmu interrupt from mring 1 = enable pmu interrupt from mring 11 r/w onevt interrupt mask pmu interrupt enable when reads, 0 = disable pmu interrupt from npmwakeup 1 = enable pmu interrupt from npmwakeup when writes to these bits, pmu interrupts will be enabling. `1' enables interrupts to the cpu, `0' masks such activity. should the enable bit be set to one when one of the debounced event signals is set, then an interrupt will be generated (i.e. the interrupt is level sensitive, not edge sensitive). 10 r/w hotsync event when reads, 0 = not hot sync state; 1 = hot sync status when writes, hotsync interrupt clear. writi ng a `1' to this bit clears the event bit 9 r/w wdtevt: watch dog reset (warm reset) when reads, 0 = no watch dog timer event occured 1 = a watch dog timer event has ocurred since last cleared when writes, watch dog reset clear. writing a `1' to this bit clears the event bit 8 r/w resetevt: warm reset event (debounced) when reads, 0 = no warm reset event has occurred 1 = a warm reset event has occurred since last cleared when writes, warm reset clear. writing a `1' to this bit clears the event bit. 7 r/w powerfailevt: adpator not ok (debounced) when reads, 0 = no power fail event since last cleared 1 = a power fail event has occurred since last cleared when writes, power fail interrupt clear. writing a `1' to this bit clears a pending interrupt bit. 6 r/w rtcevt when reads, 0 = no real time clock (rtc) calendar wake-up event since last cleared 1 = real time clock (rtc) calendar wake-up event since last cleared when writes, rtc interrupt clear. writing a `1 ' to this bit clears a pending interrupt bit. 5 r/w rievt (debounced) when reads, 0 = no modem ring indicate wake-up event since last cleared 1 = modem ring indicate wake-up event since last cleared when writes, ri interrupt clear. writing a `1 ' to this bit clears a pending interrupt bit. HMS30C7202 32 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 32 - 4 r/w onevt (debounced) when reads, 0 = no on key event since last cleared; 1 = on key event since last cleared when writes, onevt interrupt clear. writing a `1' to this bit clears a pending interrupt bit. 3 r/w plllock3 when reads, 0 = system pll has been locked since last cleared 1 = system pll has fallen out of lock since last cleared when writes, writing a `1' to this bit caus es the pll3 unlock event flag to be cleared. 2 r/w plllock2 when reads, 0 = comms pll has been locked since last cleared 1 = comms pll has fallen out of lock since last cleared when writes, writing a `1' to this bit caus es the pll2 unlock event flag to be cleared. 1 r/w plllock1 when reads, 0= lcd pll has been locked since last cleared 1= lcd pll has fallen out of lock since last cleared when writes, writing a `1' to this bit caus es the pll1 unlock event flag to be cleared. 0 r/w porstatus when reads, 0 = no por since last cl eared; 1 = por since last cleared when writes, writing a `1' to this bit c auses the npor event flag to be cleared. 5.3.4 pmu clock control register (pmuclk) this register is used to control t he frequency of pll3, the system clock pl l and pll1, the lcd clock. six bits are defined which control the frequency of fclk, and a furt her bit is used to control the frequency of pll1, the lcd clock. the default (power on reset) value for this register is 0x2126. 0x80001028 15 14 13 12 11 10 9 8 pll2 enable pll1 enable pll1 freq 7 6 5 4 3 2 1 0 pll3 mute pll3 freq update pll3 freq bits type function 31:16 - r e s e r v e d 15 r/w set for pll2 enable. output will be gated until pll2 lock detect (ld) is received. reset for disable pll2 14 r/w set for pll1 enable. output will be gated until pll1 lock detect (ld) is received. reset for disable pll1 13:8 r/w same with bit [5:0]. but output clock frequency will be half of pll3 ? default 30.4128 mhz 7 r/w reset: pll3 is muted when lock detect = 0 (default) set: pll3 only muted after npor or nrese t. subsequent unlock condition does not mute the clock. allows dynamic changes to the clock frequency without halting execution. care: this only will be legal if pll3 is under-damped (i.e. will not exhibit overshoot in its lock behavior). 6 r/w reset: pll3 frequency control frequency is only updated when pmu exits deep sleep mode (default) set: pll3 frequency control frequency is updated instantaneously 5:0 r/w value frequency value frequency 0x1b 49.7664 mhz 0x25 68.1984 mhz 0x1c 51.6096 mhz 0x26 70.0416 mhz - default 0x1d 53.4528 mhz 0x27 71.8848 mhz 0x1e 55.2960 mhz 0x28 73.7280 mhz 0x1f 57.1392 mhz 0x29 75.5712 mhz 0x20 58.9824 mhz 0x2a 77.4144 mhz 0x21 60.8256 mhz 0x2b 79.2576 mhz HMS30C7202 33 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 33 - 0x22 62.6688 mhz 0x2c 81.1008 mhz 0x23 64.5120 mhz 0x2d 82.9440 mhz 0x24 66.3552 mhz other values reserved if bit 6 is `0' when the cpu writes to bits 5:0 of th is register, these bits are stored in a temporary buffer, which is not transferred to the pll until the next time the pll lock signal becomes inactive. this means that for a new value to take effect, it is necessary for the device to enter deep sleep mode first. if bit 6 is `1' the first effect that writing a new value to bits [5:0 ] will have is that pll3 wi ll go out of lock, and the clock control circuit will immediately inhibit fclk and bclk , without first verifying that sdram operations have completed. 5.3.5 pmu debounce counter test register (pmudbct) 0x80001030 function bits type read write 31:9 - r e s e r v e d 8 w reset: normal operation set: forces fclk and blck to be active in all pmu states (test purposes only) 7:6 - reserved 5 r reserved 4 r/w selected debounce counter bits reset: normal operation set: disables bus request from the pmu to allow cpu to read state machine for test purposes during pmu idle state. 3 r/w reset: ntest takes value from input pin set: forces local test mode 2:0 r/w prescaler bits select debounce counter for value function 0x0 npmwakeup 0x1 ring event 0x3 power adapter event 0x4 warm reset in order that the debounce counter s (which would normally be clocked at 4 khz) may be independently exercised and observed, the counters may be tr iggered and observed using the above registers. these registers are for testing only and are not required in normal use. 5.3.6 pmu pll test register (pmuplltr) 0x80001038 31 ? 21 20 19 18 17 16 reserved select lclk, cclk select bclk select pll test 01(pll1), 10(pll2), 11(pll3) pll test mux 15 14 13 12 11 10 9 8 pmutest pwrdn1 pwrdn2 pwrdn3 pll1 frequency 7 6 5 4 3 2 1 0 pll3 frequency bits type function 31:21 - reserved 20 19 HMS30C7202 34 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 34 - 18:17 16 15 14 13 12 11:6 5:0 5.4 timings 5.4.1 reset sequences of power on reset figure 5-2 pmu cold reset event in the event of removal and re-application of all power to the HMS30C7202, the following sequence may be typical: z npor input is active. all internal r egisters are reset to their default values. the pmu drives nresetout low to reset any off-chip peripheral devices. z bnres becomes active on exit from the npor condition. cl ocks are enabled temporarily to allow synchronous resets to operate. z the default frequency of fclk on exit from npor will be 70.0416 mhz. z when fclk is stable, the cpu clock is re leased. if the cpu were to read the reset/status register at this time, it will return 0x10f as a initial value. z if you are to clear these flag bits, write 0x10f to the reset register. (refer 5.3.4 pmu reset/pll status register). z the cpu writes 0x20 to the clock control register, which will set a fclk speed of 58.9824mhz. the new clock frequency, however, is not adopted until the z pmu has entered and left deep sleep mode. z the cpu sets a rtc timer alarm to expire in approximately 2 seconds z the cpu sets deep sleep into the pmu mode register z the pmu state machine will enter deep sleep mode (via the intermediate states shown in figure 5-1: power management state diagram). z when the rtc timer alarm is activated, the pmu automatic ally wakes up into slow mode, but with the new fclk HMS30C7202 35 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 35 - frequency of 58.9824mhz. z the cpu may write 0xe120 to the clock control register, which enables cclk and vclk, and retains the new fclk frequency. bit meaning bit 0 set: power on reset event has occurred bit 1 set: pll1 has been `unlocked' bit 2 set: pll2 has been `unlocked' bit 3 set: pll3 has been `unlocked' table 5-2 pmu bit settings for a cold reset event within pmustat register 5.4.2 software generated warm reset figure 5-3 pmu software generated warm reset the cpu writes `1' to the warmreset bit of pmustat register. the pmu drives nreset low. the internal chip reset, bnres is driven low. the pmu detects that the bi-directional nreset pin is low. nreset is filtered by a de-bounce circuit. note that this means that nreset will remain low for a minimum of 16ms. bnres becomes active once the de-bounced nreset goes high once more, which disables pll1 and pll2. the cpu may read the pmustat register, which will return 0x106: bit meaning bit 1 set: pll1 has been `unlocked' bit 2 set: pll2 has been `unlocked' bit 8 set: a reset event has occurred. table 5-3 pmu bit settings for a software generated warm reset within pmustat register 5.4.3 an externally generated warm reset HMS30C7202 36 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 36 - figure 5-4 pmu an externally generated warm reset nreset is driven to `0' by external hardware. the nreset input is filtered by a de- bounce circuit. note that this means that nreset must remain low for a mini mum of 40ms. bnres (the on-chip reset signal) becomes active as soon as nreset is low, and high once the de-bounced nreset goes high once more. bnres disables pll1 and pll2. the cpu may read the reset register, which will return 0x106: bit meaning bit 1 set: pll1 has been `unlocked' bit 2 set: pll2 has been `unlocked' bit 8 set: a reset event has occurred. table 5-4 pmu bit settings for a warm reset within pmustat register note the internal chip reset, bnres, re mains active for 20ms after an exte rnally generated nreset. external devices should not assume that the HMS30C7202 is in an active state during this period. HMS30C7202 37 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 37 - 6 sdram controller the sdram controller operates at the full cpu core frequency (fclk = sclk) and is connected to the core via the asb bus. internally the sdram controller arbi trates between access requests from the main amba bus, and the video bus. it can control up to two sdrams of 16mx16 density maxi mum. to reduce the system power consumption it can power down these individually using the clock enable (cke). when the mcu is in standby mode the sdrams are powered down into self-refresh mode. sdrams achieve the highest throughput when accesse d sequentially ? like video data. however accesses from the core are less regular. the sdram controller uses access predictability to maximize the memory interface bandwidth by having access to the lcd address buses. video accesses to the sdram occur in fixed-burst lengths of 16 words; at each video access, sdram controller issues 4 consecutive "read" commands of whic h burst length is 8 half-word. so, if you want to get the successive 16 words, the start address of sdra m read must be arranged to 4-word(8-halfword) boundary - the start address of sdram must be 0xxxxx_xxx0. arm and dma controller accesses occur in a fixed-burst length of four words. if the requested accesses are shorter than four words, then the extra data is ignor ed. in addition, arm/dma access sdram controller discards the data of which the addr ess is not sequentially increased. for example, if arm do the 4- word "ldm(load block data)" of which start addre ss is 0x4000_0004, the address output from sdram controller to sdram is start from 2 (just 4bits from lbs). sdram do the 8-halfword burst read and it's address sequence is 2-3-4-5-6-7-0-1. in that case, s dram controller discards dat a from address 0,1 and jost get the 6-halfward data(address from 2 to 7). afte r that, sdram controller issue the "read" command again of which start address to sdram is 8 and gets the 2-halfword data(data from sdram address 8,9). features z 16 bits wide external bus interface (two access requires for each word) z supports 16/64/128/256mbit device z supports 2~64 mbytes in up to two devices (the size of each memory device may be different) z programmable cas latency z supports 2/4 banks with page lengths of 256 or 512 half words z programmable auto refresh timer z support low power mode when idle (each device?s cke is disable individually). z support external device interface with dma channel 2. 6.1 supported memory devices 2-64mbytes of sdram are supported with any combinat ion of one or two 16/64/128/256mbit devices. each device is mapped to a 32 mbyte address space. the mmu (memory management unit) maps different device combinations (e.g. 16- and 64mbit devices) into a cont inuous address space for the arm core. note that 16mbit devices appear eight times, and 64mbit devices appear twice in the memory map. total memory 16mbit devices 64mbit devices 128mbit devices 256mbit devices 2mbyte 1 - - - 4mbyte 2 - - - 8mbyte - 1 - - 16mbyte - 2 1 - 32mbyte - - 2 1 64mbyte - - - 2 HMS30C7202 38 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 38 - note the mmu (memory management unit) must be programm ed according to the actual memory configuration (combination of 16/64/128/256 mbit sdrams). the sdram controller allows up to four memory banks to be open simultaneously. the open banks may exist in different physical sdram devices. 6.2 registers the sdram controller has four registers: the confi guration, refresh timer, the write buffer flush timer and wait driver. the configuration register's main function is to specify the number of s drams connected, and whether they are 2- or 4-bank devices. the refresh timer gi ves the number of bclk ticks that need to be counted in- between each refresh period. the write buffer flush time r is used to set the number of bclk ticks since the last write operation, before the write buffer's contents are transferred to sdram. the wait driver is used to set wait delay for external slow device. address name width default description 0x8000.0000 sdcon 32 0x00700000 configuration register 0x8000.0004 sdref 16 0x0080 refresh timer 0x8000.0008 sdwbf 3 0x1 write back buffer flush timer 0x8000.000c sdwait 4 0x1 wa it driver register table 6-1 sdram controller register summary in addition to the sdram control registers, the arm may access the sdram mode re gisters by writing to a 64mbyte address space referenced from the sdram mode register base address. writing to the sdram mode registers is discussed further in ?? ! ?? ??? ?? ? ???? . ?? ! ?? ??? ?? ? ???? . 6.2.1 sdram controller configuration register (sdcon) 0x8000.0000 31 30 ? 24 23 22 21 20 19 18 17 ? 7 6 ? 3 2 ? s1 s0 - w r a c1 c0 d c b - e1 b1 - e0 b0 - bits type function 31:30 r sdram controller status 11:reserved 10:self refresh 01:busy 00:idle 24 r/w wait driver enable bit for test purpose 23 r/w normal sdram controller refresh enable 1 = the sdram controller pr ovides refresh control 0 = the sdram controller does not provide refresh 22 r/w auto pre-charge on asb accesses 1 = auto pre-charge (default) 0 = no auto pre-charge if auto pre-charge is enabled, sdram controller issues "read/write with auto pre-charge" command instead of normal "read/write" command. so, sdram controller generates "active" command before each read/write operation. if auto-pre-charge is disabled, sdram cont roller uses normal "read/write" command and sdram page that is accessed before remains active. so, sdram controller automatically issues "pre-charge" command only in the case that one sdram page is active and there is need to read/write the other page address in the same bank. you had better disable auto pre-charge bit, if a number of sdram accesses occur in the same page boundary - you can perform sdram "read/write" command fastly without "pre-charge" & "active" command. 21:20 r/w 11:cas latency3 10:cas latency2 01:cas latency1 00:reserved 19 r/w sdram bus tri-state control 0 = the controller drives the last data onto the sdram data bus (default) 1 = the sdram bus is tri-stated except during writes HMS30C7202 39 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 39 - this bit should be cleared before the ic ent ers a low power mode. driving the data lines avoids floating inputs that could increase device power consumption. during normal operation the d bit should be set, to avoid data bus drive conflicts with sdram. 18 r/w sdram clock enable control 0 = the clock of idle devices are disabled to save power (default) 1 = all clock enables are driven high continuously 17 r/w write buffer enable value = 1 if the write buffer is enabled value = 0 if the write buffer is disabled 7 r/w 1 = a device is present at address range 32-64mbyte 0 = no device present at address range 32-64mbyte the bit e is used to control the auto-refresh 6 r/w specifies the number of banks of the sdram at address range 32-64mbyte 1 = the sdram is a four-bank device 0 = the sdram is a two-bank device 3 r/w 1 = a device is present at address range 0-32mbyte 0 = no device present at address range 0-32mbyte the bit e is used to control the auto-refresh 2 r/w specifies the number of banks of the sdram at address range 0-32mbyte 1 = the sdram is a four-bank device 0 = the sdram is a two-bank device the sdram controller powers-up with e[1:0]=00 and r=0. this indicates t hat the memory interface is idle. next, the software should set at least one e bit to 1 with the r bit 0. this will cause both devices to be precharged (if present). the next operation in the init ialization sequence is to auto-refresh the sdrams. note that the number of refres h operations required is device-dependent. set r=1 and e[1:0]=00 to start the auto- refresh process. software will have to ensure that the prescribed number of refresh cycles is completed before moving on to the next step. the final step in the sequence is to set r=1 and to set the e bits corresponding to the populated slots. this will put t he sdram controller (and the sdrams) in their normal operational mode. after that sdram mode register (in the sdram, not sdcon) must be init ialized as to write burst mode = "programmed burst length", burst type = "sequential", burst length = ?8?. write e[1:0]=00 r=0 write e[1:0]=01 r=0 write e[1:0]=00 r=1 write e[1:0]=according to slot populated r=1 refresh complete? software example operation memory operation no,wait yes idle precharge auto refresh memory refreshing memory start normal operation end of initialization figure 6-1 sdram controller software example and memory operation diagram HMS30C7202 40 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 40 - 6.2.2 sdram controller refresh timer register (sdr ef) 0x8000.0004 - 15 ? 0 reserved sdref bits type function 15:0 r/w a 16-bit read/write register that is progr ammed with the number of bclk ticks that should be counted between sdram refresh cycles. for example, for the common refresh period of 16us, and a bclk frequency of 50mhz, the fo llowing value should be programmed into it: 16x10-6 * 50x106 = 800 the refresh timer defaults to a value of 128, which for a 16us refresh period assumes a worst case (i.e. slowest) clock rate of: 128/(16x10e-6) = 8 mhz the refresh register should be programmed as early as possible in the system start-up procedure, and in the first few cycles if the system clock is less than 8mhz. 6.2.3 sdram controller write buffer flush timer register (sdwbf) 0x8000.0008 - 2 - 0 reserved sdwbf bits type function 2:0 r/w a 3-bit read/write register that sets the time-out value for flushing the quad word merging write buffer. the times are given in the following table. timer value bclk ticks between time-outs 111 128 110 64 101 32 100 16 011 8 010 4 001 2 000 time-out disabled 6.2.4 sdram controller wait driver register (sdwait) 0x8000.000c - 3 ? 0 reserved sdwait bits type function 3:0 r/w this value specifies the waited delay time (blck cycles) of the bwait signal of the system bus (amba asb); default value is 1. this regist er affects only the external device with dma channel-2 operation and does not affect channel -0 and channel-1. during access to the external device with dma channel-2, write- back buffer is always enable even if sdcon (sdram controller configuration register)'s w bit (write-back buffer enable) is reset (disabling the operation of write-back buffer). 6.3 power-up initialization of the sdrams the sdrams are initialized by applying power, waiting a prescribed amount of settli ng time (typically 100us), performing at least 2 auto-refresh cycles and then writi ng to the sdram mode register. the exact sequence is HMS30C7202 41 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 41 - sdram device-dependent. the settling time is referenced from when the sdram cl k starts. the processor should wait for the settling time before enabling the sdram controller refreshes, by setting the r bit in the sdram control register. the sdram controller automatically provides an auto refres h cycle for every refresh period programmed into the refresh timer when the r bit is set. the processor must wait for sufficient time to allow the manufacturer's specified number of auto-refresh cycles befor e writing to the sdram?s mode register. the sdram's mode register is written to via its address pins (a[14:0]). hence, when the processor wishes to write to the mode register, it should read from the binary address (amba address bits [24:9]), which gives the binary pattern on a[14:0] which is to be written. the mode register of each of the sdrams may be written to by reading from a 64mbyte address space from the sdram mode register base address. the correspondence between the amba address bi ts and the sdram addre ss lines (a[14:0]) is given in the row address mapping of ?? ! ?? ??? ?? ? ???? . . bits [25] of the amba address bus select the device to be initialized. the sdram must be initialized to have the same cas la tency as is programmed in to c[1:0] bits of the sdram control register, and always to have a burst length of 8. 6.4 sdram memory map the sdram controller can interface with up to two sdrams of 1mx16, 4mx16, 8mx16 or 16mx16 density. the sdrams may be organized in either two or four banks. the controller can address 64mbyte, subdivided into two 32mbyte blocks, one for each sdrams. the mapping of the amba address bus to the sdram row and column addresses is given in ?? ! ?? ??? ?? ? ???? . . the first row of the diagram indica tes the sdram controller address output (sa[14:0]) and the sdram address bit (bs1, bs0,a12~a0); if you use 64mbit sdram, you should connect a11~a0 to sa[11:0] and bs0~1 to sa[13:12]. the remaining numbers indicate the amba address bits mba[24:1]. sdram addr sa[14] a12 sa[13] bs0 sa[12] bs1 sa[11] a11 sa[10] a10 sa[9] a9 sa[8] a8 sa[7] a7 sa[6 a6 sa[5] a5 sa[4 a4 sa[3] a3 sa[2] a2 sa[1] a1 sa[0] a0 row 16mbit 24 10* 9* 22 20* note 1 19* 18* 17* 16* 15* 14* 13* 12* 11* col 16mbit 24 10* 9* note1 20 note 1 23 8* 7* 6* 5* 4* 3* 2* note2 row 64mbit 24 10* 9* 22* 20* 21* 19* 18* 17* 16* 15* 14* 13* 12* 11* col 64mbit 24 10* 9* 22 20 21 23 8* 7* 6* 5* 4* 3* 2* note2 row 128mbit 24 10* 9* 22* 20* 21* 19* 18* 18* 16* 15* 14* 13* 12* 11* col 128mbit 24 10* 9* 22 20 21 23* 8* 7* 6* 5* 4* 3* 2* note2 row 256mbit 24* 10* 9* 22* 20* 21* 19* 18* 18* 16* 15* 14* 13* 12* 11* col 256mbit 24 10* 9* 22 20 21 23* 8* 7* 6* 5* 4* 3* 2* note2 mode write 24* 10* 9* 22* 20* 21* 19* 18* 17* 16* 15* 14* 13* 12* 11* summary 24 10 9 22 20 21 19/23 18/8 17/7 16/6 15/5 14/4 13/3 12/2 11* table 6-2 sdram row/column address map notes (1) for the 16mbit device, sdram address line a11 should be connected to the HMS30C7202 pin sa[13](bs0), and the sdram address line a9 should be connected to the hms3 0c7202 pin sa[12](bs1). the HMS30C7202 address lines sa[11] and sa[9] should not be connected. (2) since all burst accesses commence on a word boundary, and sdram addresses are non-incrementing (the address incremented is internal to the device), column addr ess zero will always be driven to logic `0'. * an asterisk denotes the address lines that are used by the sdram. the start address of each sdram is fixed to a 32mbyte boundary. the memory management unit will be used HMS30C7202 42 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 42 - to map the actual banks that exist in to contiguous memory as seen by the arm. bits [25] of the amba address bus select the device to be initialized, as described in ?? ! ?? ??? ?? ? ???? . . a25 device selected 0 device 0 1 device 1 table 6-3 sdram device selection 6.5 amba accesses and arbitration the sdram controller bridges both the amba main and video buses. on the main bus, the sdram appears as a normal slave device. on the video dma bus, the s dram controller integrates the functions of the bus arbiter and address decoder. writes from the main bus may be merged in the quad word merging write buffer. a main/video arbiter according to the following sequence ar bitrates access requests fr om either the main or video buses: highest priority: lcd refresh request lowest priority: main bus peripheral (pmu, arm, dma)--order determined by main bus arbiter. video sdram accesses always occur in bursts of 16 word s. once a burst has star ted, the sdram controller provides data without wait states. video data is onl y read from sdram, no write path is supported. if a refresh cycle is requested, then it will have lower pr iority than the video bus, but will be higher than any other accesses from the main bus. assuming a worst-ca se bclk frequency of 8mhz, the maximum, worst- case latency that the arbitration sc heme enforces is 11.5us before a refr esh cycle can take place. this is comfortably within the 16us limit. no te that the 2 external sdram devic es are refreshed on 2 consecutive clock cycles to reduce the peak current demand on the power source. the arbitration of the main bus is left to the main bu s arbiter. data transfers requested from the main bus always occur as a burst of eight half-word accesses to sdram. the main bus arbiter cannot break into access requests from the main bus. in the case where fewer than four words are actually requested by the main bus peripheral, the excess data from the sdram is ig nored by the sdram controller in the case of read operations, or masked in the case of wr ites. in the case where more than f our words are actually requested by the main bus peripheral, the sdram controller asserts blast to force t he asb decoder to break the burst. in the case of word/half-word/byte misalignment to a quad word boundary (when any of address bits [3:0] are non-zero at the start of the transfer), blast is assert ed at the next quad word boundary (bits 3, 2, 1 and 0 properly set 1 for each type) to force the asb decoder to break the burst. sequential half word (or byte) reads are supported and the controller asserting blast at quad word boundary. in the case of byte or half word reads, data is replicated across the whole of the asb data bus. data bus for word access: 31 23 15 7 0 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data bus for half word access: 31 23 15 7 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data bus for byte access: 31 23 15 7 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 6.6 merging write buffer an eight word merging write-buffer is implemented in the sdram controller to improve write performance. the write buffer can be disabled, but its operation is completely transpar ent to the programmer. the eight words of the buffer are split into two quad words, the same size as all data transactions to the sdrams. the HMS30C7202 43 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 43 - split into two quad words allows one quad word to be wri tten to at the same time as the contents of the other are being transferred to sdram. the quad word buffer currently being written to may be accessed with non- contiguous word, half word or byte writes, which will be merged into a single quad word. the buffered quad word will be transferred to the sdram when: z there is a write to an sdram address outside the current quad word being merged into z there is a read to the address of the quad word being merged into z there is a time-out on the write back timer the two quad-words that make up the write buffer operat e in "ping-pong" fashion, whereby one is initially designated the buffer for writes to go into, and the other is the buffer for write backs. when one of the three events that can cause a write-back o ccurs, the functions of the two buffe rs are swapped. thus the buffer containing data to be written back becomes the buffer that is currently writing back, and the buffer that was the write-back buffer becomes the buffer being written to. in the case of a write-back initiated by a read from t he same address as the data in the merge buffer, the quad word in the buffer is written to sdram, and then t he read occurs from sdram. the write before read is essential, because not all of the quad word in the buffer may have been updated, so its contents need to be merged with the sdram contents to fill any gaps wher e the buffer was not updated. the write buffer flush timer forces a write back to occur after a programmable amount of time. every time a write into the buffer occurs, the counter is re-loaded with the programmed time -out value, and starts to counts down. if a time-out occurs, then data in the write buffer is written to sdram. HMS30C7202 44 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 44 - 7 static memory interface the static memory controlle r (smi) interfaces the amba advanced system bus (asb) to the external bus interface (ebi). it controls four separate memory or ex pansion banks. each bank is 32mb in size and can be programmed individually to support: z 8-, 16- or 32-bit wide, little-endian memory z variable wait states (up to 16) z burst mode read access burst mode access allows fast sequential access within quad word boundaries. this can significantly improve bus bandwidth in reading from memory (that mu st support at least four word burst reads). in addition, bus transfers can be extended using the exprdy input signal. 7.1 external signals pin name type description exprdy i expansion channel ready. when low, during phase one this signal will force the current memory transfer to be extended. nrwe [3:0] o these signals are active low writ e enables for each of the memory byte lanes on the external bus. nroe o this is the active low output enable for devices on the external bus. nrcs [3:0] o active low chip selects. ra [24:0] o rom address bus rd [31:0] i/o rom data bus bootsbit [1:0] i configuration input. 00 - select bank 0 as 32-bit memory 01 - select bank 0 as 16-bit memory 10 - select bank 0 as 8-bit memory 11 - reserved 7.2 functional description the main functions of the static memory controller (smi) are : z memory bank select z access sequencing z wait states generation z burst read control z byte lane write control these are described below 7.2.1 memory bank select start address address (hex) size description 0 mbytes 0x0000.0000 32mbytes rom chip select 0 64 mbytes 0x0400.0000 32mbytes rom chip select 1 128 mbytes 0x0800.0000 32mbytes rom chip select 2 192 mbytes 0x0c00.0000 32mbytes rom chip select 3 7.2.2 access sequencing the bank configuration also determines the width of t he external memory devices. when the external memory bus is narrower than the transfer initiated from the curr ent master, the internal transfer will take several external bus transfers to complete. for example, in ca se that memory bank0 is configured as 8-bit wide HMS30C7202 45 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 45 - memory and a 32-bit read is initiated the amba bus sta lls while the smi read four consecutive bytes from the memory. during these accesses the data path is controll ed (in the ebi) to demultiplex the four bytes into one 32-bit word on the amba asb bus. 7.2.3 wait states generation the static memory controller supports wait states fo r read and write accesses. this is configurable between one and 16 wait states for standard memory access, and ze ro and 15 wait states for burst mode. the static memory controller also allows transfers to be extended indefinitely, using the exprdy signal. to hold the current transfer, exprdy must be low on the falling edge of bclk before the last cycle of the accesses. the transfer cannot complete until exprdy is high for at least one cycle. 7.2.4 burst read control up to four consecutive locations in 8-, 16- or 32-bit memories can be read in one burst. if the bus width of external memory is less than that of internal bus, you have to set the value of burst read wait state in 7.3.1 mem configuration register more than 1 cycle for stable data transfers between them. 7.2.5 byte lane write control this controls nrwe [3:0] according to transfer widt h, ba [1:0] and the access sequencing. the table below shows nrwe coding case by little endian ac cessing to 32,16,8-bit external memory bus. case1. access: write, 32-bit external bus bsize [1:0] ba [1:0] nrwe [3:0] 10(word) xx 0000 01(half) 1x 0011 0x 1100 00(byte) 11 0111 10 1011 01 1101 00 1110 case2. access: write, 16-bit external bus bsize [1:0] ba [1:0] ia [1:0] *1 nrwe [3:0] 10(word) xx 1x 1100 xx 0x 1100 01(half) 1x 1x 1100 0x 0x 1100 00(byte) 11 1x 1101 10 1x 1110 01 0x 1101 00 0x 1110 case3. access: write, 8-bit external bus bsize [1:0] ba [1:0] ia [1:0] *1 nrwe [3:0] 10(word) xx 11 1110 xx 10 1110 xx 01 1110 xx 00 1110 01(half) 1x 11 1110 1x 10 1110 HMS30C7202 46 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 46 - 0x 01 1110 0x 00 1110 00(byte) 11 11 1110 10 10 1110 01 01 1110 00 00 1110 note *1 ia [1:0] : internal smi address 7.3 registers address name width default description 0x8000.3000 memcfg0 0x0 memory configuration register 0 0x8000.3004 memcfg1 0x0 memory configuration register 1 0x8000.3008 memcfg2 0x0 memory configuration register 2 0x8000.300c memcfg3 0x0 memory configuration register 3 table 7-1 static memory controller register summary 7.3.1 mem configuration register 11 10 9 8 7 6 5 4 3 2 1 0 bur en burst read wait state normal access wait state mem width bits type function 31:12 - r e s e r v e d 11 r/w burst enable. setting this bit enables burst reads to take advantage of faster access times from memory devices that support burst mode. 10:7 r/w value 1111 1110 ? 0001 0000 number of burst read wait state 0 1 ? 14 15 (default) 6:3 r/w value 1111 1110 ? 0001 0000 number of normal access wait state 1 2 ? 15 16 (default) 2 - reserved 1:0 r/w value 11 10 01 00 memory width reserved 8 bit memory access 16 bit memory access 32 bit memory access HMS30C7202 47 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 47 - 7.4 examples of the smi read, write wait timing diagram the following timing diagrams show sequential and non-sequential read and write accesses. for information on the amba bus internal signals re fer to the amba specification (arm ihi 0011a) 7.4.1 read normal wait (non-sequential mode) this timing diagram shows a non-sequential read accesses with 5 wait cycles (mem config register = 0x058). * note 1.4 bclk nrc nroe a r r d btra n nonseq_tran a ba dsel x bwai t d(a) the amba bus internal signals * note 1.1 * note 1.2 * note 1.3 the smi control signals *note 1.1: bwait time = bclk x 5 wait cycle *note 1.2: valid the smi address latch on the asb bus address when ba and dsel are valid condition. *note 1.3: after generated smi control signals and the end of 5wait cycles, external device read data is valid with smi address (ra), nrcs, and nroe. *note 1.4: external memory access time. it is the same as wait time (i.e. bwait cycle time = 5 wait cycle) HMS30C7202 48 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 48 - 7.4.2 read normal wait (sequential mode) this timing diagram shows a sequential read accesses with 3 wait cycles (mem config register = 0x068) a_tran bclk nrcs nroe ra r d btran a ba dselx bwait d(a) s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran a_tran a+4 a+8 a+c a a+4 a+8 a+c note *1.4 note *1.4 note *1.4 note *1.4 note *1.5 note *1.6 note *1.7 note *1.7 note *1.7 note *1.5 note *1.5 note *1.5 the amba bus internal signals the smi control signals d(a+4) d(a+8) d(a+c) burst enable ?l? *note 1.4: bwait time = bclk x 3 wait cycle (if mcr is set) *note 1.5: valid the smi address latch on the asb bus address when ba and dsel are valid condition. *note 1.6: after generated smi control signals, external device read data is valid with smi address(ra), nrcs, and nroe. *note 1.7: the btran is sequential transfer so the smi control signal (nrcs, nroe) are not asserted any more, and then external device read da ta is valid with smi address (ra). HMS30C7202 49 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 49 - 7.4.3 read burst wait (sequential mode) this timing diagram shows a sequential burst read accesses with 3 wait cycles (mem config register = 0xe60) above the figure of burst wait signals ; make sure that burstenable signal will be change (high to low) at the ba is become to different value. a_tran bclk nrcs nroe ra r d btran a ba dselx bwait s_tran s_tran s_tran a note *1.8 note *1.9 burst enable s_tran a+c s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran a_tran a+4 a+8 a+4 a+8 a+c note *1.8.1 note *1.8.1 note *1.8.1 note *2.0 note *2.1 note *2.1 note *2.1 note *1.9 note *1.9 note *1.9 the amba bus internal signals the smi control signals d(a) d(a+4) d(a+8) d(a+c) *note 1.8 : for the 1 s t read of a burst read transfer the wait time is normal wait time (in this example 4 cycles). *note 1.8.1: bwait time = bclk x 3 wait cycle(if mcr is set) *note 1.9: valid the smi address latch on the asb bus address when ba, dsel, and burstenable are valid condition. *note 2.0: after generated smi control signals, extern al device read data is valid with smi address (ra), nrcs, and nroe. *note 2.1: the btran is sequential transfer so the smi control signal (nrcs, nroe) are not asserted any more, and then external device read da ta is valid with smi address(ra). HMS30C7202 50 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 50 - 7.4.4 write normal wait (sequential mode) this timing diagram shows a sequential write accesses with 3 wait cycles (mem config register = 0x068). a_tran bclk nrcs nrwe ra r d btran a b a dselx bwait d(a) s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran s_tran a_tran a+4 a+8 a+c a a+4 a+8 a+c note *2.2 note *2.2 note *2.2 note *2.2 note *2.3 note *2.4 note *2.5 note *2.5 note *2.5 note *2.3 note *2.3 note *2.3 the smi control signals d(a+4) d(a+8) d(a+c) bwrite the amba bus internal signals *note 2.2: bwait time = bclk x 3 wait cycle (if mcr is set) *note 2.3: valid the smi address latch on the asb bus address when ba and dsel are valid condition. *note 2.4: after generated smi contro l signals, external device write data is valid with smi address (ra), nrcs, and nrwe. *note 2.5: the btran is sequential transfer so nrcs exte rnal chip enable signal is not asserted, but nrwe external write enable signal asserted on the falling edge of bclk. HMS30C7202 51 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 51 - 7.5 internal sram 7.5.1 remapping enable register HMS30C7202 allows the remapping of the internal sram block (base address : 0x7f00.0000 - 2kb size) to enhance the performance. 0x8000.1040 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 reserved 15 14 13 12 11 10 9 8 reserved remap size 7 6 5 4 3 2 1 0 remap size reserved remapen bits type function 31:13 - r e s e r v e d 12:3 r/w remap size (word boundary) caution : max size of remapping is 0x7ff(2kb area). if remap size setting exceeds this value, the correct operation can not be guaranteed 2:1 reserved 0 r/w 1 : enable remap 0 : disable remap 7.5.2 remap source address register 0x8000.1048 31 30 29 28 27 26 25 24 reserved 23 22 21 20 19 18 17 16 remap source address 15 14 13 12 11 10 9 8 remap source address 7 6 5 4 3 2 1 0 remap source address reserved bits type function 31:25 - r e s e r v e d 24:2 r/w remap source address start address of remapping(word boundary) 0:1 reserved HMS30C7202 52 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 52 - 8 lcd controller features z single panel color and monochrome stn displays z tft color displays z resolution programmable up to 640x480 z single panel mono stn displays with either 4- or 8-bit interfaces z 15 gray-level mono support, 3375 color stn support z 4bpp mono, 4 or 8bpp palletized color displays z 16bpp color `true-color' color displays(tft) z programmable timing for different display panels z 3 x 256 entry, 5-bit red, blue and 6-bit green palette ram in tft mode z 3 x 256 entry, 4-bit palette ram in stn mode z patented grayscale algorithm z little-endian operation note the controller does not support dual panel stn displays. there is no hardware cursor support, since wince does not use a cursor. 8.1 video operation a block diagram of the video system is shown in fi gure 8-1: video system block diagram. the video system has a data path for stn lcd and for tft lcds. figure 8-1 video system block diagram dma master fifo video fifo videounpack palette (3x256x4) videopalettel lcd gs lcd format lcdoutfifo register & palette fast apb slave lcdtiming lcdcogen bclk vclk lclk cp lp fp ac ld[15:0] format[7:0] rgs, ggs, bgs r, g, b pixelred[4:0] pixelgreen[5:0] pixelblue[4:0] videodma l armfifo32 fifo read valid flag fifo write fifo r/w signal vba[25:5] vbd[31:0] vgn t vreg bclk pa[11:2] pd[31:0] psel pstb pwrite HMS30C7202 53 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 53 - 8.1.1 lcd datapath in tft mode the digital rgb data is directly available at output pins. however, in stn mode, the data must be gray scaled, and then formatted for the lcd panel. the grayscaler block converts the 4 bit per color gun data into a single bit per gun, using a patented time/space dither algorithm. in mono mode, only the b gun data is used. the output of the grayscaler is fed to the formatter, which formats the pixels in the correct order for the lcd panel type in use. (4 or 8 mono pixels per clock for mono panels, or 2 2/3pixels per clock for color data.) the output of the formatter in color mode is bursty, due to the 2 2/3pixels per clock that are output, so the formatter output goes to a small fifo, which smoothes ou t this burstiness, before data is output to the lcd panel at a constant rate. 8.1.1.1 palette ram & 16bpp mode logical pixels are either 8 or 16 bits. in 8-bit mode, the lo gical pixel value is used to index into the three palette arrays to select the three color components of the phys ical pixel value. in 16-bit pseudo true-color mode, a patented technique is used to allow 2 16 colors to be selected from 2 24 possible colors. se parate color gun values are independently used to index into the three pa lette arrays, to select an 8-bit value for each of the color guns. by splitting the palette ram into three sepa rate ram arrays, it allows 16-bit mode to generate 8- bit color gun data. the method used is an arm patented technique, where 16bpp data is split into three over- lapping 8-bit fields that are used to index into the thr ee ram arrays. the red gun is indexed by bits 15:8 of the 16-bit pixel value, the blue gun is indexed by bits 7:0 of the pixel value, and the green gun is indexed by bits 11:4 of the pixel value. by programming the palette with the correct values, 5:5:5, 5:6:5, 4:8:4, and many other combinations of 16-bit data may be used. thus: 8 bpp : 256 palette entries are used for each palette array. all three palette rams are indexed by pixel[7:0] 16 bpp : 256 palette entries are used for each palette array. red array is indexed by pixel[15:8], green array is indexed by pixel[11:4], and blue array is indexed by pixel[7:0] figure 8-2 shows 5:6:5 combination. le ast significant 3bits are don?t cares for red index, most significant 3bits are don?t cares for blue index. bit0 and bit7 are don?t cares for green index. figure 8-2 5:6:5 combination of 16bpp data the effective 5, 6, and 5 bits are indexes to hms 30c7202 palette ram for tft mode. figure 8-3 shows HMS30C7202 palette register mapping for 16bpp(5:6:5) representation. HMS30C7202 54 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 54 - figure 8-3 palette ram entries for 5:6:5 combination to program palette ram as in figure 8-3, refer to the code in figure 8-4. unsigned long palette[256]; main ( ) { int i; for (i=0; i<256; i++) { // store 5 bits red, 6 bits green, and 5 bits blue palette[i] = ((i &0x1f) << 19) | ((i&0x7e) << 9) | ((i&0xf8)); printf(?%d, %02x, %02x, %02x \r\n? , i, (i&0x1f) << 3, (i&0 x7e) << 1, (i&0xf8) << 0 ); } } figure 8-4 sample code for 5:6:5 palette generation HMS30C7202 55 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 55 - 8.1.2 color/grayscale dithering entries selected from the look-up palette are sent to the color/grayscale space/time base dither generator. each 4-bit value is used to select one of 15 intensity levels. note that two of the 16 dither values are identical. t he table below assumes that a pixel data input to the lcd panel is active high. that is, a `1' in the pixel data stream will turn the pixel on, and a `0' will turn it off. if this is not the case, the intensity order will be reversed, with "0000" being the mo st intense color. this polarity is lcd panel dependent. the gray/color intensity is controlled by turning indivi dual pixels on and off at varying periodic rates. more intense grays/colors are produced by making the averag e time that the pixel is off longer than the average time that it is on. the proprietary di ther algorithm is optimized to provide a range of intensity values that match the eye's visual perception of color/gray gradations, with smaller changes in intensity nearer to the mid-gray level, and greater nearer the black and the white levels. in color mode, red, green and blue components are gray-scaled simultaneously as if they were mono pixels . the duty cycle and resultant intensity level for all 15 color/grayscale levels is summarized in table 8-1: color/grayscale intensities and modulation rates. dither value (4 bit value from palette) intensity (0% is white) modulation rate (ration of on to on+off pixels) 1111 100.0 1 1110 100.0 1 1101 88.9 8/9 1100 80.0 4/5 1011 73.3 11/15 1010 66.6 6/9 1001 60.0 3/5 1000 55.6 5/9 0111 50.0 1/2 0110 44.4 4/9 0101 40.0 2/5 0100 33.3 3.9 0011 26.7 4/15 0010 20.0 1/5 0001 11.1 1/9 0000 0.0 0 table 8-1 lcd colorgrayscale intensities and modulation rates 8.1.3 how to order the bit on ld[7:0] output in stn mode, the low order ld signals are the first pixe ls on the line, and the high order ld signals are later pixels on the line. in color mode things are different once again. ld[7] is the red component of the first pixel on the line, and ld[6] is the green component of the pixel, and ld[5] the blue, with ld[4] being the red component of the next pixel. this pattern continues, with ld[0] being the gr een component of the third pixel, and ld[7] of the next clock being the blue component of the same pixel. HMS30C7202 56 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 56 - lcd pin time sequence ld[7] r0 b2 g5 r8 ? r0 b2 ld[6] g0 r3 b5 g8 ? g0 r3 ld[5] b0 g3 r6 b8 ? b0 g3 ld[4] r1 b3 g6 r9 ? r1 b3 ld[3] g1 r4 b6 g9 ? g1 r4 ld[2] b1 g4 r7 b9 ? b1 g4 ld[1] r2 b4 g7 r10 ? r2 b4 ld[0] g2 r5 b7 g10 ? g2 r5 table 8-2 how to order the bit on ld[7:0] in 8-bit color stn mode 8.1.4 tft mode when tft display mode is enabled, the timing of the pi xel, line and frame clocks as well as the ac-bias pin change. the pixel clock transitions continuously in this mode as long as the lcd is enabled. the ac-bias pin functions as an output enable. when it is high, the display latches data from the lcd's pins using the pixel clock. the line clock pin is used as the horizontal sy nchronization signal (hsync), and the frame clock is used as the vertical synchronization si gnal (vsync). pixel data is output one pixel per clock, rather than 4, 8 or 22/3pixels per clock, as it is in the passive lcd modes. 8.2 registers address name width default description 0x8001.0000 lcdcontrol lcd control register 0x8001.0004 lcdstatus lcd status register 0x8001.0008 lcdstatusm lcd status mask register 0x8001.000c lcdinterrupt lcd interrupt register 0x8001.0010 lcddbar lcd dma channel base address register 0x8001.0014 lcddcar lcd dma channel current address register 0x8001.0020 lcdtiming0 lcd timing 0 register 0x8001.0024 lcdtiming1 lcd timing 1 register 0x8001.0028 lcdtiming2 lcd timing 2 register 0x8001.0040 lcdtest lcd test register 0x8001.0044 gsfstate grayscaler production test register 0x8001.0048 gsrstate grayscaler production test register 0x8001.004c gscstate grayscaler production test register 0x8001.0400~ 0x8001.07fc lcdpalette lcd palette programming registers table 8-3 lcd controller register summary 8.2.1 lcd power control lcd displays require that the lcd is running before power is applied. fo r this reason, the lcd's power on control is not set to "1" unless both lc den and lcdpwr are set to "1". note that most lcd displays require the lcden must be set to "1" approximatel y 20ms before lcdpwr is set to "1" for powering up. likewise, lcdpwr is set to "0" 20ms before lcden is set to "0" for powering down. 0x80010000 24 ldbusen 23 22 21 19 18 lcdble lcdpwr lcdmono8 lcdvcomp 12 bgr HMS30C7202 57 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 57 - 4 3 2 1 0 lcdtft lcdbw lcdbpp lcden bits type function 31:25 - r e s e r v e d 24 r/w ld data bus enable 0 ? ld data bus disabl e (initial value) 1 ? ld data bus enable 23 r/w lcd backlight enable this drives "0" or "1" out to the lcd backlight enable pin 22 r/w lcd power enable 0 - lcd is off 1 - lcd is on when lcden=1 21 r/w lcd monochrome data width 0 - 4 bits lcd module 1 - 8 bits lcd module 20 - reserved 19:18 r/w generate interrupt at: 00 - start of vsync 01 - start of back porch 10 - start of active video 11 - start of front porch 17:13 - r e s e r v e d 12 r/w 0 - rgb normal video output for lcd 1 - bgr red and blue swapped for lcd 11:5 - reserved 4 r/w lcd tft 0 - passive or stn display operation enabled 1 - active or tft display operation enabled 3 r/w lcd monochrome 0 - color operation enabled 1 - monochrome operation only enabled 2:1 r/w lcd bits per pixel 00 - 4bpp 01 - 8bpp 10 - 16bpp 11 ? reserved 0 r/w lcd controller enable 0 - lcd controller disabled 1 - lcd controller enabled 8.2.2 lcd controller status/mask and interrupt registers the lcd controller status, mask and interrupt register s all have the same format. each bit of the status register is a status bit that may generate an interr upt. the corresponding bits in the mask register mask the interrupt. the interrupt register is the logical and of the status and mask register s, and the interrupt output from the lcd controller is the logical or of the bits within the interrupt register. the lcd controller status regi ster contains bits that signal an under-run error fo r the fifo, the dma next base update ready status, and the dma done status. each of these hardware- detected events can generate an interrupt request to the interrupt controller. 0x80010004 ~ 0x800100c 3 2 1 0 ldone vcomp lnext lfuf bits type function 31:4 - reserved 3 r lcd done frame status/mask/interrupt bit the lcd frame done (done) is a read-only status bit that is set after the lcd has been HMS30C7202 58 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 58 - disabled (lcden = 0) and the frame that is curre nt active finishes being output to the lcd's data pins. it is cleared by writing the base address (lcddbar) or enabling the lcd, or, by writing "1" to the ldone bit of the status r egister. when the lcd is disabled by clearing the lcd enable bit (lcden=0) in lcdcontrol, the lcd allows the current frame to complete before it is disabled. after the last set of pixels is clocked out onto the lcd's data pins by the pixel clock, the lcd is disabled and done is set. 2 r/w vertical compare interrupt this bit is set when the lcd timing generator re aches the vertical region programmed in the video control register. this bit is "sticky", meani ng it remains set until it is cleared by writing a "1" to this bit 1 r lcd next base address update status/mask/interrupt bit the lcd next frame (lnext) is a read-only status bit that is set after the contents of the lcd dma base address register are transferred to the lcd dma current address register at the start of frame, and it is cleared when the lcd dma base address register is written. 0 r/w fifo underflow status/mask/interrupt bit the lcd fifo underflow (lfuf) status bit is set when the lcd fifo under-runs. the status bit is "sticky", meaning it remains set after the fifo is no longer underrunning. the status bit is cleared by writing a `1' to this bit. 8.2.3 lcd dma base address register the lcd dma base address register (lcddbar) is a read /write register used to specify the base address of the off-chip frame buffer for the lcd. addresses prog rammed in the base address register must be aligned on sixteen-word boundaries, thus the leas t significant six bits (lcddbar [5:0]) must always be written with zeros. only 26 bits of the register are valid (including the ls 6 bits which must be zero), because lcd dma is only allowed from sdram. the 26 bits address range allows the lcd dma to a ccess any address within the sdram. the upper address lines are not needed, because these are the address lines used to select which device is accessed, but the lcd always accesses sdram. the user must initialize the base address register before enabling the lcd, and may also write a new value to it while the lcd is enabled to allow a new frame buffer to be used for the next frame. the user can change t he state of lcddbar while the lcd c ontroller is active, after the next frame (next) status bit is set within the lcd's status register that generates an in terrupt request. this status bit indicates that the value in the base address point er has been transferred to the current address pointer register and that it is safe to write a new base address value. this allows double-buffered video to be implemented if required. 0x80010010 bits type function 31:26 - reserved. keep these bits zero 25:6 r/w lcddbar : lcd dma channel base address pointer 16-word aligned base address in sdram of the frame buffer within off-chip memory. 5:0 - reserved. keep these bits zero 8.2.4 lcd dma channel current address register this read-only register allows the processor to r ead the current value of t he lcd dma channel current address register. this is not something that would normall y be done, but it allows additional test observability. its value cannot be expected to be exact, it could change at an moment. however, its contents can be read to determine the approximate line that t he lcd controller is currently displaying and driving out to the display 0x80010014 bits type function 31:26 - reserved. keep these bits zero 25:6 r/w lcddcar : lcd dma channel current address pointer 16-word aligned current address pointer to data in sdram frame buffer currently being displayed 5:0 - reserved. keep these bits zero 8.2.5 lcd timing 0 register lcd timing 0 register (lcdtiming0) controls horizontal lcd timing. see 8.6.2 pixel clock divider (pcd) on HMS30C7202 59 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 59 - page 8-13 for a description of the terms "pixelclock" and "lcdclk" 0x80010020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hbp hfp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 hsw ppl bits type function 31:24 r / w horizontal back porch the 8-bit horizontal back porch (hbp) field is used to specify the number of pixel clock periods to insert at the beginning of each line or row of pixels. after the line clock for the previous line has been negated, the value in hbp is used to count the number of pixel clocks to wait before starting to output the first set of pixels in the next line. hbp generates a wait period ranging from 1-256 pixel clock cycles (n umber of lcdclk clock periods to add to the beginning of a line transmission before the first set of pixels is out put to the display minus 1). 23:16 r / w hfp horizontal front porch the 8-bit horizontal front porc h (hfp) field is used to spec ify the number of pixel clock periods to insert at the end of each line or row of pixels before pulsing the line clock pin. once a complete line of pixels is transmitted to the lcd driver, the value in hfp is used to count the number of pixel clocks to wait before pulsi ng the line clock. hfp generates a wait period ranging from 1-256 pixel clock cycles. (program to value required minus one). 15:8 r/w horizontal sync pulse width the 6-bit horizontal sync pulse width (hsw) field is used to specify the pulse width of the line clock in passive mode, or horizontal synchroniza tion pulse in active mode. number of lcdclk clock periods to pulse the line clock at the end of each line minus 1 7:2 r/w the pixels-per-line (ppl) bit-field is used to specify the number of pixels in each line or row on the screen. ppl is a 6-bit value that repres ents between 16-1024 pixels per line. ppl is used to count the correct number of pixel clocks that must occur before the line clock can be pulsed. program the value requi red divided by 16, minus 1. 1:0 - reserved 8.2.6 lcd timing 1 register lcd timing 1 register (lcdtiming1) controls lcd vertical timing parameters. 0x80010024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 vbp vfp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vsw lps bits type function 31:24 r / w vertical back porch the 8-bit vertical back porch (vbp) field is used to specify the number of line clocks to insert at the beginning of each frame, i.e. number of i nactive lines at the start of a frame, after vsync period. the vbp count starts just afte r the vsync signal for the previous frame has been negated for active mode, or the extra line clocks have been inserted as specified by the vsw bit-field in passive mode. after this has o ccurred, the value in vbp is used to count the number of line clock periods to insert before st arting to output pixels in the next frame. vbp generates from 0-255 extra line clock cycles. th is should be programmed to zero in passive mode, unless sensing lcd to vga to share dma data 23:16 r / w vertical front porch the 8-bit vertical front porch (v fp) field is used to specify the number of line clocks to insert at the end of each frame, i.e. number of inactive lines at the end of frame, before vsync period. once a complete frame of pixels is trans mitted to the lcd display, the value in vfp is used to count the number of line clock periods to wait. after the count has elapsed the vsync (lcdfp) signal is pulsed in active mode, or ex tra line clocks are inserted as specified by the vsw bit-field in passive mode. vfp generates from 0-255 line clock cycles. this should be zero for passive display modes, unless synchronizing to the vga to share data. HMS30C7202 60 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 60 - 15:10 r / w vertical sync pulse width the 6-bit vertical sync pulse widt h (vsw) field is used to specify the pulse width of the vertical synchronization pulse in active mode, or is used to add extra dummy line clock delays between frames in passive mode. should be small for passive lcd, but should be long enough to re-program the video palette under interrupt control, without writing the video palette at the same time as video is being di splayed. the register is programmed with the number of lines of vsync minus one. 9:0 r/w lines per screen the lines per screen (lps) bit-fi eld is used to specify the number of lines or rows per lcd panel being controlled. lps is a 10-bit value that represents 1-1024 lines per screen. the register is programmed with the number of lines per screen minus 1. 8.2.7 lcd timing 2 register lcd timing 2 register (lcdtiming2) controls various functi ons associated with the timing of the lcd controller. 0x80010028 27 26 25 24 23 22 21 20 19 18 17 16 skip4 bcd cpl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 slv ieo ipc ihs ivs acb lcs pcd bits type function 31:28 - r e s e r v e d 27 r/w set this bit to "1" when running a color passive lcd with slave mode. this produces an irregular clock to the lcd, where every fourth clock pulse is suppressed (the clock stays low for one clock period). this is necessary because tw o-and-two-third pixels per clock, which are sent to the lcd, is not an integer multiple. this means that three clocks will be output every four-clock period. if pcd is zero, then eight pixels will be output every eight lcdclk periods, since the lcd cp clock will be half the frequency of lcdclk. 26 r/w bypass pixel clock divider setting this bit allows an undivided lcd clock to be output on lcd. this bit could only be set for tft mode but not in normal cases. 25:16 r / w clocks per line this is the actual number of clocks output to the lcd panel each line, minus one. this must be programmed, in addition to the ppl field in the lcd timing 0 register. the number of clocks per line is the number of pixels per line divided by 1, 4, 8 or two-and-two-thirds for tft mode, mono 4-bit mode, mono 8-bit, or color stn mode (22/3) respectively. 15 r/w slave mode slave (or genlock) lcd to vga video. the hsync and vsync are locked to the vga timing generator. the lcd horizontal timing must be carefully programmed if sharing dma data 14 r/w invert output enable the invert output enable (ieo) bit is used to se lect the active and inactive state of the output enable signal in active display mode. in this mo de, the ac-bias pin is used as an enable that signals the off-chip device when data is actively being driven out using the pixel clock. when ieo=0, the lcdac pin is active high. when ieo= 1, the lcdac pin is active low. in active display mode, data is driven onto the lcd's data lines on the programmed edge of lcdcp when lcdac is in its active state. 0 - lcdac pin is active high in tft mode 1 - lcdac pin is active low in tft mode 13 r/w invert pixel clock the invert pixel clock (ipc) bit is used to se lect which edge of the pixel clock pixel data is driven out onto the lcd's data lines. when ipc=0, data is driven onto the lcd's data lines on the rising-edge of lcdcp. when ipc=1, data is driven onto the lcd's data lines on the falling- edge of lcdcp. 0 - data is driven on the lcd's da ta lines on the rising-edge of lcdcp. 1 - data is driven on the lcd's data lines on the falling-edge of lcdcp. 12 r/w invert hsync the invert hsync (ihs) bit is used to invert the polarity of the lcdlp signal. 0 - lcdlp pin is active high and inactive low. HMS30C7202 61 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 61 - 1 - lcdlp pin is active low and inactive high. 11 r/w invert vsync the invert vsync (ivs) bit is used to invert the polarity of the lcdfp signal. 0 - lcdfp pin is active high and inactive low. 1 - lcdfp pin is active low and inactive high. 10:6 r/w ac bias pin frequency the 5-bit ac-bias frequency (acb) field is used to specify the number of line clock periods to count between each toggle of the ac-bias pin (lcd ac). this pin is used to periodically invert the polarity of the power supply to prevent dc charge build-up within the display. the value programmed is the number of lines between transitions, minus 1. note the acb bit field had no effect on lcdac in active mode. the pixel clock transitions continuously in active mode and the ac bi as line is used as an output enable signal 5 r/w lcd clock source selection 0 - dma bus clock (system bus clock) 1 - video pll clock (vclk; in normal operation) 4:0 r/w pixel clock divisor used to specify the frequency of the pixel cloc k based on the lcd clock (lcdclk) frequency. pixel clock frequency can range from lcdclk/2 to lcdclk/33, where lcdclk is the clock selected by lcs. pixel clock frequency = lcdclk/(pcd+2). note that in the case of the lcd, the pixel clock is not the frequency of some nominal clock rate that individual pixels are output to the lcd. it is the frequency of the lcdcp signal. in normal mono mode (4-bit interface), four pixels are output per lcdcp cycle, so the pixelclock is one quarter the nominal pixel rate. in the ca se of 8-bit interface mono, pixelclock is one- eighth the nominal pixel rate, since 8 pixels are ou tput per lcdcp cycle. in the case of color, pixelclock is 0.375 times the nominal pixel ra te, because 22/3 pixels are output per lcdcp cycle. if the lcd and vga are operating concurrently, and sharing dma data, then in color mode the pixel clock should normally be 3/8 the vga clock. to achieve this, pcd should be 7programmed to the value 0 and the skip4 bit set to "1". the skip4 bit produces a null clock cycle (no high phase) every fourth clock cycle. 8.2.8 lcd test register the lcd test register contains bits that allow certai n lcd signals to be output on the lcd pins for test purposes. this register should not no rmally be used. the register is reset to all zero, and this will result in normal operation. 0x80010040 8 tcount 7 6 5 4 3 2 1 0 tcc tlc tcr tlr tcf trf tldata test mode bits type function 31:9 - reserved 8 r/w separates the 10-bit counter into nibbles for the test purpose 7 r / w for production test of grayscaler, never writ e a "1" to these registers in normal use. 6 r/w for production test of grayscaler, never writ e a "1" to these registers in normal use. 5 r/w for production test of grayscaler, never writ e a "1" to these registers in normal use. 4 r/w for production test of grayscaler, never writ e a "1" to these registers in normal use. 3 r/w for production test of grayscaler, never writ e a "1" to these registers in normal use. 2 r/w for production test of grayscaler, never writ e a "1" to these registers in normal use. 1 r/w walking one's pattern used in place of sdram data for the lcd controller 0 r/w test mode bit for grey-scaler 8.2.9 grayscaler test registers the registers gsframe state, gsrow state and gs colu mn state are used for the purpose of production test HMS30C7202 62 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 62 - and must not be written to or read from in normal use. 0x80010044, 0x80010048, 0x8001004c 8.2.10 lcd palette registers the lcd palette registers are a set of 256 word-aligned registers that allow the lcd to be programmed. the format of the palette data is shown below. at the tft mode, the palette ram bit width will be increased as figure 8-6. 0x80010400 23 22 21 20 b 15 14 13 12 7 6 5 4 g r figure 8-5 lcd palette word bit field for stn mode 23 22 21 20 19 b 15 14 13 12 11 10 7 6 5 4 3 g r figure 8-6 lcd palette word bit field for tft mode HMS30C7202 63 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 63 - 8.3 timings figure 8-7 example mono stn lcd panel signal waveforms figure 8-8 example tft signal waveforms, start of frame figure 8-9 example tft signal waveforms, end of last line HMS30C7202 64 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 64 - 9 fast amba peripherals 9.1 dma controller this chip includes a three-channel direct memory access controller (dmac). high-speed transfers between peripheral devices and the sdram can be controlled by t he dmac instead of the cpu core. transfers using addresses other than sdram will produce unpredictable results. features z three channels. z max transfer rate: 133mb/s. z max buffer size: 16383. z address mode: single(sdram) address is supported. z channel function: transfer modes are different in each channel. i. channel 0: dedicated to the sound interface controller. this channel has a source address reload function. the memory space of the sound i/o device consis ts of a double buffer. the sound interface uses exception bus mode and word access. the channel performs only dma transfers for transmitting data (transfe rs from sdram to the sound interface). ii. channel 1: dedicated to the smc/mmc interface block. the channel uses exception bus mode and word access. it controls dma transfers for both transmitting (from sdram) and receiving (to sdram). word is the only supported tr ansfer size. correct dma operation of this channel is guaranteed only if the sdram wr ite buffer is enabled and lcd operation is disabled. otherwise it will produce unpredictable results. iii. channel 2: used by external io device. the channel supp orts both exception and burst bus modes. transfer sizes of byte, half word (16 bits) and word are all supported. z channel priority: configured by register setting. z interrupt request: the dmac interrupt request can be triggered by each channel whenever the dma transfer is completed by buffer size. since only one interrupt id is assigned to the dmac, the interrupt flag register (flagr) mainta ins the information on which dma channel requested the interrupt. z the channel 2 should not be enabled with eit her of the other channels at the same time. 9.1.1 external signals pin name type description ndmareq i dma request input signal from exter nal device (level sens itive, active low) ndmaack o dma acknowledge output signal to external device. 9.1.2 registers address name width default description 0x8000.4000 adr0 32 0x0 write: start address of the first buffer of channel 0 read: current address of the first buffer of channel 0 0x8000.4004 asr 32 0x0 write: start address of the second buffer of channel 0 read: current address of the second buffer of channel 0 0x8000.4008 tnr0 14 0x3fff write: size of the first buffer of channel 0 (in words) read: number of words in the first buffer of channel 0 which remain to be transferred 0x8000.400c tsr 14 0x3fff write: size of the second buffer of channel 0 (in words) read: number of words in the second buffer of channel 0 which remain to be transferred 0x8000.4010 ccr0 4 0x0 channel 0 control 0x8000.4014 adr1 32 0x0 write: start address of channel 1 buffer read: current address of channel 1 buffer 0x8000.4018 tnr1 14 0x3fff write: size of channel 1 buffer (in words) read: number of words in channel 1 buffer which remain to be transferred HMS30C7202 65 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 65 - 0x8000.401c ccr1 3 0x0 channel 1 control 0x8000.4020 adr2 32 0x0 write: start address of channel 2 buffer read: current address of channel 2 buffer 0x8000.4024 tnr2 14 0x3fff write: size of channel 2 buffer (in unit of transfer size). read: number of data in channel 2 buffer which remain to be transferred (in unit of transfer size) 0x8000.4028 ccr2 8 0x0 channel 2 control 0x8000.4038~ 0x8000.4040 - - - reserved 0x8000.4044 flagr 5 0x0 dma interrupt flags 0x8000.4048~ 0x8000.4050 - - - reserved 0x8000.4054 dmaor 3 0x0 operation control of the dmac table 9-1 dma controller register summary 9.1.2.1 adr0 0x8000.4000 31 30 29 ? 2 1 0 adr0 bits type function 31:0 r/w write: start address of the first buffer (buffer 0) of channel 0 (for the sound interface) read: current address of the first buffer of channel 0 9.1.2.2 asr 0x8000.4004 31 30 29 ? 2 1 0 asr bits type function 31:0 r/w write: start address of the second buffer (buffer 1) of channel 0 read: current address of the second buffer of channel 0 9.1.2.3 tnr0 0x8000.4008 - 13 12 ? 1 0 reserved tnr0 bits type function 13:0 r/w write: size of the first buffer of channel 0 (in words, max. 16383 ) read: number of words in the first buffer of channel 0 which remain to be transferred 9.1.2.4 tsr 0x8000.400c - 13 12 ? 1 0 reserved tsr bits type function 13:0 r/w write: size of the second buffer of channel 0 (in words, .max. 16383 ) read: number of words in the second buffer of channel 0 which remain to be transferred 9.1.2.5 ccr0 0x8000.4010 - 2 1 0 reserved mask01 mask00 dmen0 bits type function HMS30C7202 66 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 66 - 2 r/w buffer 1 transfer end interrupt mask bit of channel 0 1 = interrupt request is generated when the whole dma transfer of buffer 1 is completed. 0 = no interrupt request is generated when the whole dma transfer of buffer 1 is completed. 1 r/w buffer 0 transfer end interrupt mask bit of channel 0 1 = interrupt request is generated when the whole dma transfer of buffer 0 is completed. 0 = no interrupt request is generated when the whole dma transfer of buffer 0 is completed. 0 r/w channel 0 enable bit 1 = channel 0 is enabled. 0 = channel 0 is disabled. 9.1.2.6 adr1 0x8000.4014 31 30 29 ? 2 1 0 adr1 bits type function 31:0 r/w write: start address of channel 1 buffer (for smc/mmc) read: current address of channel 1 buffer 9.1.2.7 tnr1 0x8000.4018 - 13 12 ? 1 0 reserved tnr1 bits type function 13:0 r/w write: size of channel 1 buffer (in words, max. 16383 ) read: number of words in channel 1 buffer which remain to be transferred 9.1.2.8 ccr1 0x8000.401c - 2 1 0 reserved mask1 mode1 dmen1 bits type function 2 r/w transfer end interrupt mask bit of channel 1 1 = interrupt request is generated when the dma transfer of the whole buffer is completed. 0 = no interrupt request is generated when the dma transfer of the whole buffer is completed. 1 r/w transfer direction 0 = transfer from sdram to smc/mmc 1 = transfer from smc/mmc to sdram 0 r/w channel 1 enable bit 1 = channel 1 is enabled. 0 = channel 1 is disabled. 9.1.2.9 adr2 0x8000.4020 31 30 29 ? 2 1 0 adr2 bits type function 31:0 r/w write: start address of channel 2 buffer (for external i/o device) read: current address of channel 2 buffer 9.1.2.10 tnr2 0x8000.4024 - 13 12 ? 1 0 reserved tnr2 HMS30C7202 67 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 67 - bits type function 13:0 r/w write: size of channel 2 buffer (in unit of transfer size, max. 16383 ) read: number of data in channel 2 buffer which remain to be transferred (in unit of transfer size) 9.1.2.11 ccr2 0x8000.4028 - 8 7 6 5 4 3 2 1 0 reserved isa burst type size mask2 mode2 dmen2 bits type function 8 r/w external bus type 0: not isa type (default) 1: isa type 7:6 r/w burst length 11: 32 beats 10: 16 beats 01: 8 beats 00: 4 beats 5 r/w transfer type 0: exception mode 1: burst mode 4:3 r/w transfer size 11: reserved 10: word 01: half word 00: byte 2 r/w transfer end interrupt mask bit of channel 2 1 = interrupt request is generated when the dma transfer of the whole buffer is completed. 0 = no interrupt request is generated when the dma transfer of the whole buffer is completed. 1 r/w transfer direction 0 = transfer from sdram to external i/o 1 = transfer from external i/o to sdram 0 r/w channel 2 enable bit 1 = channel 2 is enabled. 0 = channel 2 is disabled. * note: the burst mode must be used in the external bus type of isa 9.1.2.12 flagr 0x8000.4044 - 3 2 1 0 reserved flag2 flag1 flag01 flag00 bits type function 3 r/w interrupt flag of channel 2 set when the whole transfer of channel 2 buffer is completed. if mask2 (bit 2 of ccr2) is set, there is an interrupt request. 2 r/w interrupt flag of channel 1 set when the whole transfer of channel 1 buffer is completed. if mask1 (bit 2 of ccr1) is set, there is an interrupt request. 1 r/w interrupt flag of the first buffer of channel 0 set when the whole transfer of the first buffer of channel 0 is completed. if mask01 (bit 2 of ccr0) is set, there is an interrupt request. 0 r/w interrupt flag of the second buffer of channel 0 set when the whole transfer of the second buffer of channel 0 is completed. if mask00 (bit 1 of ccr0) is set, there is an interrupt request. note: each flag bit is cleared by writing ?1? to its bit position . 9.1.2.13 dmaor 0x8000.4054 - 2 1 0 reserved prmd dmaen bits type function 2:1 r/w defines the channel priorities in case of simultaneous transfer requests for multiple channels. 11: ch0 > ch1 > ch2 10: ch2 > ch1 > ch0 01: ch1 > ch0 > ch2 00: ch1 > ch2 > ch0 (initial value) HMS30C7202 68 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 68 - 0 r/w dma operation enable bit 1 = dma operation is enabled. 0 = dma operation is disabled. a specific dma channel is enabled when both of this bit and the corresponding channel enable bit (dmenx) are set. 9.1.3 dmac operation for correct dma operation, the dma address register (a drx or asr), dma buffer size register (tnrx), dma channel control register (ccrx), a nd dma operation register (dmaor) must be set properly. then the dmac performs dma data transfers as follows. z the dmac checks if the corresponding channel enable bit (dmenx, bit 0 of ccrx) and the dmaen (bit 0 of dmaor) are enabled. z when there is a transfer request fr om internal or external i/o and the dma transfer in the corresponding channel is enabled, the dmac initia tes dma data transfers according to the bus size, transfer direction and bus mode. z the dmac ends data transfers and sets the correspon ding interrupt flag (flagx of flagr) when the whole buffer is transferred (when the internal count val ue equals tnrx or tsr). if the interrupt mask bit of the channel is set (and the dma interrupt is enabled in the interrupt controller), a dma transfer end interrupt request is sent to the cpu core. dma channel priority when the dmac receives simultaneous dma transfer requests , the channel with the higher priority is served first. the channel priorities are programmable in the dmaor register. dma bus mode burst mode (for channel 2) once the bus mastership is obtain ed, the transfer is performed contin uously by the burst length (burst, bit 7 of ccr2) as long as ndmareq pin is driven hi gh. then the bus mastership is given to the cpu. exception mode (cycle-steal mode) in the exception mode, the bus mast ership is given to the cpu core whenever one transfer is completed dma transfer request the dma transfer request should be disabled by i/o device module. HMS30C7202 69 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 69 - 9.2 mmc/ spi controller the spi is a high-speed synchronous serial port. this chapter describes the spi communication with a mmc device. the communication between cp (master) and mmc is controlled by the cp. the data transmission starts when the cs (chip-select) goes low and ends when the cs goes high. spi-mmc messages are built from command, response and data-block tokens. every command, response and data block is built with one byte (8-bit). general ly every mmc token transferred on the data signal is protected by crc bits. but mmc offers also a non-protec ted mode that allows a system, built with reliable data links to exclude the hardware or firmware required for crc generation and verification. in the non-protected mode, the crc bits of the command, response and data tokens are still required in the tokens; they are, however, defined as "don't care" fo r the transmitters and are ignored by the receivers. mmc is initialized in the non-protected mode. the cp can turn this option on and off using the crconoff command (cmd39). we assume that crc is processed by software. 9.2.1 external signals pin name type description ssdo o mmc card controller data output ssdi i mmc card controller data input ssclk o mmc card controller clock output nsscs o mmc card controller chip select 9.2.2 registers (spi mode) address name width default description 0x8001.5000 spicr 0x20 spi control register 0x8001.5004 spisr 0x0 spi status register 0x8001.5008 xchcnt 0x0 number of exchange data 0x8001.500c txbuff 0x0 tx data buffer (8*8 bits) 0x8001.5010 rxbuff 0x0 rx data buffer (8*8 bits) 0x8001.5014 testreg1 0x0 test register 1 0x8001.5018 testreg2 0x0 test register 2 0x8001.501c resetreg 0x0 spi reset register 0x8001.5024 ticreg 0x0 tic register table 9-3 spimmc controller register summary 9.2.2.1 spimmc control register (spicr) 0x8001.5000 6 5 4 3 2 1 0 datarate cs xchmode testmode loop spien xch bits type function 7 - reserved 6 r/w this bit sets the baud rate (spiclk) 0 : spiclk=bclk/2 1 : spiclk=bclk/4 5 r/w this bit is the chip select signal. to communi cate with external devices (mmc), cp asserts 0 in this bit. 0 = cp can exchange data with external device (mmc) 1 = cp cannot exchange data with external device (mmc) 4 r/w this bit determines the direction of transfer 0 = cp have valid data to send to mmc (send mode) 1 = cp have valid data to receive from mmc (receive mode) 3 r/w 0 = normal operation 1 = the spi-mmc block is in tic mode. in this mode the clock source is not bclk/2 but tclk that is made in the block. HMS30C7202 70 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 70 - 2 r/w 0 = normal operation 1 = the spi-mmc block is in loopback mode in the loopback mode the transmitter output is internally connected to the receiver input. miso is internally connected to mosi. 1 r/w 0 = spi master disable (reduce power consumption) 1 = spi master enable the spi must be enabled before initiating an exchange and should be disabled after the exchange is complete to reduce the power consumption. 0 r/w this bit triggers the state machine to generate clocks at the selected bit rate. 1 = initiate exchange 0 = no exchange occurs 9.2.2.2 spimmc status register (spisr) 0x8001.5004 7 6 5 txet xchdone rxfull bits type function 7 r when the tx data buffer is empty this bit is se t and a serial peripheral interrupt is generated. the bit is reset by reading the spisr. 6 r when the exchange is completed between cp an d mmc this bit is set and a serial peripheral interrupt is generated. the bit is reset by reading the spisr. 5 r when the rx data buffer is full this bit is se t and a serial peripheral interrupt is generated. the bit is reset by reading the spisr. 4:0 - reserved 9.2.2.3 spimmc xch counter register (xchcnt) 0x8001.5008 9 8 7 6 5 4 3 2 1 0 xch counter bits type function 9:0 r/w number of bytes to be exchanged between cp and spi 9.2.2.4 spimmc tx data buffer register (txbuff) 0x8001.500c this 8-bit register is the entry point of the tx fifo. when cp writes an 8-bit data to this register, the spi-mmc block shifts the content of the tx fifo and appends the new data to the fifo. 7 6 5 4 3 2 1 0 tx fifo entry point bits type function 7:0 w tx fifo?s entry point 9.2.2.5 spimmc rx data buffer register (rxbuff) 0x8001.5010 this register is the access point of the rx fifo. when cp reads one data item from this register, the spi- mmc block shifts the rx fifo so that the next data item becomes available at this location. 7 6 5 4 3 2 1 0 rx fifo access point bits type function 7:0 r rx fifo?s access point HMS30C7202 71 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 71 - 9.2.2.6 spimmc reset register (resetreg) 0x8001.501c 0 reset bits type function 7:1 - reserved 7:0 r/w when cp writes 0 to this location, a ll registers and counters of the spi-mmc block are cleared. 9.2.3 timings all timing diagrams use the following schematics and abbreviations. name description name description h signal is high (logic 1) busy busy token l signal is low (logic 0) command command token x don?t care response response token z high impedance state datablk data token * repeater all timing values are defined as outlined below. command/response host command to card re sponse: card is ready cs h h l l l ************************************************************ l l h h h n cs mosi h h h h h h 6 bytes command h h h h h *************** h h h h x x x n cr miso z z z h h h h *************** h h h h h response h h h h h z z host command to card re sponse: card is busy cs h h l l l ************************************************************ l l l l h h h n cs mosi h h h h h h 6 bytes command h h h h h *************** h h h h x x x n cr miso z z z h h h h *************** h h h h h response busy * busy h h z z card response to host command: cs l l l l l ************************************************************ l l h h h mosi h h h h h h *************** h h h h h 6 bytes command h h h h x x x n rc miso h h h h h response h h h h h *************** h h h h h z z data read cs h h l l l ************************************************************ l l h h h n cs mosi h h h h h h read command h h h h h *************** h h h h x x x n cr n ac miso z z z h h h h h h h h response hh hh datablk h h h h h z z HMS30C7202 72 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 72 - data write cs h h l l l ************************************************************ l h h h n cs n wr mosi h h h h h h write command h h h h h ******* datablk h ************* x x x n cr miso z z z h h h h h h h h response h h h h * h h h data resp. busy h z z timing constants definitions name minimum maximum unit n cs 0 - 8 clock cycles n cr 1 2 8 clock cycles n rc 1 - 8 clock cycles n ac 1 - 8 clock cycles n wr 1 - 8 clock cycles 9.2.4 spi operation for mmc after cp writes a sequence of data to the tx fifo, the c ontent of the fifo is loaded into the tx shift register and shifted out serially one byte at a time. when all el ements in the tx fifo are transferred to the tx shift register, the spi-mmc issues an interrupt to cp, whic h may fill the tx fifo for further data transfer. serial input data is shifted into the rx shift register. after 8 bits are shifted in, the content of the rx shift register is copied into the rx fifo. when the rx fifo is full, the spi-mmc issues an interrupt to cp through the spiirq signal. cp reads the content of the rx fifo in an interrupt service routine. the timing and control blo ck produces all necessary control signals of the spi -mmc block including spiclk. the frequency of spiclk signal is programmable. spi-mmc transfer's protocol is command and response. whenever cp sends a command to mmc (via spi), mmc sends cp (via spi) a response. the length of t he response depends on the command ? e.g. there are 1-, 6-, and 17-byte responses. there is only 6 bytes in command. consider the sequence of operations that occur in a read transfer. 1. cp sends a reset signal to the spi-mmc block. in other word, cp writes "0 " to bit in the re setreg register. the signal is used to clear counters inside the blo ck. before new exchange begins and the content of xchcounter is changed, and transmit mode is changed (xchmode bit in the spicr), cp must send a reset signal to the spi-mmc block. 2. first, cp set up the spicr register. in this example, xchmode is send mode. 3. cp writes number to send into xchcounter register. 4. cp writes "data read command (cmd17)" into the tx fifo. 5. cp asserts cs signal. in other word s, cp write 0 to cs bit in the spicr. 6. cp sends a start signal to spi-mmc. in other word, cp set xch bit in the spicr. 7. the spi-mmc block sends out 6 bytes of command da ta from tx fifo through tx shift register. 8. the spi-mmc block issues the interrupt after it send all data in tx fifo. 9. the cp reads the spisr register in the spi-mmc block and disable start signal (reset xch bit). in other words, cp writes the spicr register. 10. cp sends a reset signal to the spi -mmc block. in other word, cp writes 0 to bit in the resetreg register. the signal is used to clear counters inside the blo ck. before new exchange begins and the content of xchcounter is changed, and transmit mode is changed (xchmode bit in the spicr), cp must send a reset signal to the spi-mmc block. 11. cp changes transmit mode (xchmode is receive mode). 12. the cp writes number to be received into xchcounter register. 13. cp sends a start signal to spi-mmc (set xch bit). 14. then spi-mmc controller receives response from mmc. 15. after spi-mmc receives 1 byte (for cmd17 command), it sets xch done status bits and it issues an interrupt to a cp. 16. the cp reads the spisr register in the spi-mmc block and disable st art signal (reset xch bit). in other words, cp writes the spicr register. 17. the cp reads data rx fifo. HMS30C7202 73 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 73 - 18. after cp takes this response data and examine it, cp ac t as response data. if there is no error indication in response, cp informs spi-mmc blo ck that mmc sends data to it. 19. cp sends a reset signal to the spi-mmc block. in other words, cp writes 0 to bit in the reset register. the signal is used to clear counters inside the block. before new exchange begins and the content of xchcounter is changed, and transmit mode is changed (xchmode bit in the spicr), cp must send a reset signal to the spi-mmc block. 20. the cp writes number to be received into xchcounter register. 21. cp sends a start signal to spi-mmc (set xch bit). 22. the spi-mmc block receives data from mmc (for ex ample, data length is from 4 byte to 515 byte). 23. if spi-mmc receives data like rx fifo size, spi-mmc bl ock sets the "rx fifo full" status bit and issues an interrupt to cp. at this time spiclk disable start si gnal for prevention of rx fifo overrun. if cp takes all data in rx fifo, cp sends a start signal and receives response to remain. repeat it. 24. after spi-mmc block receive all data from mmc, it se ts the xch done status bit and issues an interrupt to cp. 25. the cp reads the spisr register in the spi-mmc block and disable st art signal (reset xch bit). in other words, cp writes the spicr register. 26. after cp takes last data from rx fifo, cp de-asserts cs signal. 9.2.5 multimedia card host controller this document will describe the basic operation about the mmc host controller for the arm7202. this controller operates in mmc mode to communicate with multimedia card. 9.2.6 registers the mmc host controller has 12 registers. following table shows the register map and its reset value. address name width default description 0x8001.5040 mmcmodereg 9 mmc mode register 0x8001.5044 mmcoperationreg 9 mmc operation register 0x8001.5048 mmcstatusreg 15 mmc status register 0x8001.504c mmcintrenreg 7 mmc interrupt enable register 0x8001.5050 mmcblocksizereg 11 mmc block size register 0x8001.5054 mmcblocknumberreg 16 mmc block number register 0x8001.5058 mmctimeperiodreg 24 mmc time period register 0x8001.505c mmccmdbufferreg 6 mmc command buffer register 0x8001.5060 mmcargbufferreg 32 mmc arg buffer register 0x8001.5064 mmcrespbufferreg 32 mmc resp buffer register 0x8001.5068 mmcdatabufferreg 32 mmc data buffer register 0x8001.507c mmcreadytimeoutreg 24 mmc ready timeout register table 9-4 mmc host controller register summary 9.2.6.1 mmc mode register 0x8001.5040 8 7 6 5 : 3 2 1 0 intrreq dmareq softreset clkrate dmaen reserved enable bits type function 8 r interrupt request signal. 7 r dma request signal. 6 r/w software reset. 5:3 r/w clock rate divisor value. bclk is 50mhz. mmcclk speed will be one of these values according to divisor value. 0 for 25mhz (1/2 bclk) 1 for 12.5mhz (1/4 bclk) 2 for 6.25mhz (1/8 bclk) 3 for 3.125mhz (1/16 bclk) HMS30C7202 74 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 74 - 4 for 1.5625mhz (1/32 bclk) 5 for 0.78125mhz (1/64 bclk) 6 for 0.390625mhz (1/128 bclk) 7 for 0.1953125mhz (1/256 bclk) 2 r/w dma enable. 1 - reserved 0 r/w mmc enable. table 9-5 mmc mode register mmc controller can be reset by the two methods. first is the system reset. in this case, most registers are initialized to the default value. but two registers (re sponse fifo and data fifo) are not initialized. second is the software reset. it is accomplished by writing the 7th bit of mmc mode control regist er with 1. its effect is same with the first. following table shows the mmc mode control register. this controller sends the dma request signal in two case s (rx & tx). and if you want to use dma, you must set the dmaen bit of mmc mode regist er. for rx, when the number of data in the fifo is more then zero, it generates the request signal. for tx, when the number of data in the fifo are less then eight, it generate the request signal. operation frequency can be controlled by setting the clkrate bit of mmc mode register. divisor controls the rate of mmc clock (mmcclk). assume that bclk has 50mhz frequency. 9.2.6.2 mmc operation register 0x8001.5044 8 7 6 5 4:3 2 1 0 busycheck streamen writeen dataen respformat initialization clken starten bits type function 8 r/w current command needs the busy check after command operation. 7 r/w define stream mode( 1 = stream mode, 0 = block mode ) 6 r/w 1 = write, 0 = read. default is read 5 r/w indicate that current command contains the data operation 4:3 r/w response format (no response, r1, r2, and r3) 0 for no response 1 for format r1 2 for format r2 3 for format r3 2 r/w add the 128 clocks before sending the command 1 r/w enable the clock 0 r/w/c start the mmc operation table 9-6 mmc operation register all multimedia cards require at least 74 clock cycl es prior to starting bus communication. and the clock frequency must be less then the open- drain frequency(f_od=0.5mhz). theref ore the host controller must do these during power-on. for generating 74 clock cycles, set initialization bit of mmc operation register. if initialization bit is set, then the controller will send additional 128 clocks before send start bit. although this bit is zero, the controller sends 16 clocks before the start bit for safe operation. and add 8 clocks after the stop bit. mmc has the four types of the response (no response , r1, r2, and r3). and each format is similar to the command format. but you need not know what they shap e. you just only need to know the length of response to be stored after the response end. r1 and r3 have on e word. and r2 has four words. its contents are different according to the each command. you must an alysis this content according to the each command after operation. and the response format can be specif ied by the respformat bits of the operation control register. 9.2.6.3 mmc status register 0x8001.5048 14 13 12 11 10 9 8 detected_n detintr readytimeout respcrcerr datacrcerr resptimeout datatimeout 7 6 5 4 3 2 1 0 HMS30C7202 75 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 75 - cardbusy dataoperend datatransend cmdrespend clkonv rxfifofull txfifoempty rxfifoready bits type function 14 r card detection status 13 r/wc card detection interrupt 12 r/wc ready timeout error status 11 r/wc response data crc error 10 r/wc rx or tx data crc error 9 r/wc response timeout error 8 r/wc data timeout error 7 r card busy status 6 r/wc mmc operation status 5 r/wc data transfer status for rx and tx 4 r/wc command response end status 3 r clock status 2 r rx fifo is full 1 r tx fifo is empty 0 r rx fifo contains more than the one word table 9-7 mmc status register wc : to clear these bit, you need to write any dummy value to these register . 9.2.6.4 mmc interrupt enable register 0x8001.504c 6 5 4 3 2 1 0 mmcdetintr crcerrintr timeoutintr oprendintr datatranfendintr cmdrespendintr datafifointr bits type function 6 r/w card detection interrupt (insertion, remove). this interrupt can be used to check the card insertion and removal 5 r/w crc errors interrupt (response crc error, data crc error). this interrupt is generated in two cases (response crc error, data crc error). if crc interrupt is generated, mmc host controller will stop the current operation. 4 r/w timeout interrupt (response timeout, data timeout, and ready timeout). mmc host controller generates three types of timeout interrupt (response, data, and busy). these three timeout values are specified in mmc time period register and mmc ready timeout register. isr can check the each timeout interrupt by reading mmc status register. 3 r/w operation end interrupt. this interrupt is generated when all operation is finished. before the start operation, you need to set mmc operation register. this register contains information about the operation. if an operation does not need the response and data, this interrupt is generated after the end of command transfer. if an operation just needs response, it is generated when mmc host controller receives the response. if an operat ion needs the data operation, it is generated when mmc host controller finish all operation including busy checking. 2 r/w data transfer end interrupt. this interrupt is generated when mmc host contro ller receives or sends the data specified by mmc block size register and mmc block number register. in most case, multimedia card goes into the ready state to write internal buffer data into flash memory. so after data transfer, multimedia card can be ready state for some ti me. this interrupt can be used to inform the data transfer end without busy check. 1 r/w command response ends interrupt. this interrupt is generated when mmc host controller finishes receiving of command response. for data read operation, because t he response and data is transmitted currently, you can user this interrupt to check t he data fifo and the response fifo independently. 0 r/w data fifo interrupt (rx fifo full,tx fifo empty). this interrupt is generated in two cases (rx fifo full, tx fifo empty). you can use this interrupt to check the fifo status during the read and write operation. and by reading the status register, you can know which interrupt is taken. table 9-8 mmc interrupt enable register HMS30C7202 76 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 76 - mmc host controller has the seven interrupt sources (r x/tx fifo interrupt, command response interrupt, data transfer end interrupt, mmc operation interrupt, tim eout interrupt, crc error interrupt and mmc detection interrupt). setting the each interrupt enable bit of mmc in terrupt enable register can enable each interrupt. we can consider the card detection in the two cases. firstly, in case that mmc host controller is not enab led, clock is not supplied into the controller. so the detection logic can operate without t he clock. to detect the mmc without cl ock, the detection signal is passed into the interrupt request directly. if the card detection in terrupt is enabled, interrupt signal will be passed into the interrupt controller. secondly, if mmc host controller is enabled; it means the de tection logic now operates with clock. in this case, mmc host controller detects bot h card insertion and card removal. when this interrupt is generated, you can detect if current interrupt is the card insertion or removal by reading the detected_n bit of mmc status register. if the value is zero, it indica tes card insertion. if not, it notifies card removal. 9.2.6.5 mmc block size register 0x8001.5050 10 ? 0 max. block length bits type function 10:0 r/w maximum block length definition up to 2048 bytes. table 9-9 mmc block size register 9.2.6.6 mmc block number register 0x8001.5054 15 ? 0 max. number of block bits type function 15:0 r/w maximum number of block transfer definition up to 64k blocks. table 9-10 mmc block number register 9.2.6.7 mmc time period register 0x8001.5058 23 ? 16 15 ? 0 resptimeout datatimeout bits type function 23:16 r/w response timeout period 15:0 r/w data timeout period table 9-11 mmc time period register 9.2.6.8 mmc command buffer register 0x8001.505c 5 ? 0 command buffer bits type function 5:0 r/w command buffer table 9-12 mmc command buffer register 9.2.6.9 mmc argument buffer register 0x8001.5060 31 ? 0 argument buffer bits type function 31:0 r/w argument buffer HMS30C7202 77 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 77 - table 9-3-6-9 mmc argument buffer register 9.2.6.10 mmc response buffer register 0x8001.5064 31 ? 0 response buffer bits type function 31:0 ro response buffer table 9-13 mmc response buffer register this controller has two fifo, which are response and dat a fifo. each has 4-word depths and 8-word depths. and both fifos are cleared at the start of the command. if there were some data before starting, incorrect data will be transmitted, so you have to confirm that the fifo is empty to writing any value into the status register. there is no way to write the mmc resp buffer directly. this register can be written only when the response from mmc card is received. for data fifo, it used two modes. if the current operation is read, it will be used the rx fifo, if not, the tx fifo. 9.2.6.11 mmc data buffer register 0x8001.5068 31 ? 0 data buffer bits type function 31:0 r/w data buffer table 9-14 mmc data buffer register 9.2.6.12 mmc ready timeout register 0x8001.507c 23 ? 0 readytimeout bits type function 23:0 r/w ready timeout period table 9-15 mmc ready timeout register 9.2.7 basic operation in mmc mode mmc command format consists of six parts. four pa rts (start bit, transmitter bit, crc, and stop bit) are automatically generated by mmc host controller. for remain two parts (command index, argument), you must inform the mmc host controller by setting registers properly. after power-on, all multimedia cards need at least 74 clo ck cycles prior to starting the operation. it can be achieved by setting the third bit (initialization) of the mmc operation register. if set, mmc host controller sends 128 clock cycles prior to sending start bit. in case of data operation, you need to define the type of operation. for example, at the case of block write, both dataen and writeen are '1'. to enable stream read, both dataen and streamen are '1' while writeen is ?0?. for some command, it needs the busy check after the command end. in this case, busy check bit of mmc operation register is must be set (for more deta ils, refer to "multimedia card product manual"). finally, to initiate operation, write '1' to starten and clken. then mmc host controller starts to send command to multimedia cards. and starten bit is cleared automatically when the mmc host controller finishes current operation. clken bit makes mmc clock to be enabled. in this case, the mmc clock (mmcclk) is generated during the operation. if this bit is zero, cl ock to operate control bl ock is not generated. HMS30C7202 78 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 78 - you can check the end of response or oper ation from mmc status register. this register also contains lots of useful information about what mmc host controller is doing. if the current operation does not c ontain data operation, you just need to poll cmdrespend or dataoperend bit. but if not, you need to have another step prior to starting. if current command requires multiple block operation, you must inform the block l ength and the number of block to be transferred to mmc host controller. these controllers (mmcblocksizereg, mmcblocknumberr eg) can specify up to 2048 bytes for the length of block, and 64k blocks for the number of block. following shows the procedure for the write and read operation. 9.2.7.1 write operation mmc host controller starts the sending of data at the end of response end. and if the controller does not receive response during a specified period, it will generat e response timeout error. anyway, after the response end, if tx fifo is not ready (fifo is empty), waits until the data is ready. the data transfer can be done by the three methods (polling, interrupt, and dma (direct me mory access)). polling method checks the tx fifo empty bit of the status register and if it is empty, you can write less than the eight word. and again wait until tx fifo is empty. repeat this proced ure until the operation end bit is set. interrupt method uses the tx fifo empty interrupt. for every interrupt, you can write the eight words. and exit the isr (i nterrupt service routine). and then wait for the next interrupt. dm a method uses not arm720t core but the dma controller, so you must program the dma controller before start operation. mmc host controller must set the dmaen bit of mmc mode register. dma request signal is generated whenever t he number of data in tx fifo is less then equal to seven. 9.2.7.2 read operation multimedia card can send both response and data currently after receiving the command from the host controller. so, mmc host controller wa its the response and data at the same time. therefore, you must check response and data concurrently. or you can use the response end interrupt. but in most case, after the response end, you can start read data from the rx fifo. this is reason why the rx fifo sizes with the eight words (32*8 cycles), so to fill it, the controller needs the 256 cycles. the data transfer also can be done by the three methods like the write operation. polling method chec ks the rx fifo ready bit of the status register. this bit is activated when rx fifo has more than two word data. so you just read two times when you check this bit is set. interrupt method uses the rx fifo full in terrupt. because the rx fifo has eight word depths, whenever interrupt is called, isr reads the eight words fo rm the rx fifo. in the case of the rx fifo full, you don't worry about it because the mmc ho st controller stops t he output clock not to loss on the bus. in dma mode, the dma request is generated when the rx fifo has one more words. * note: errata sheet (version 1.0) includes contents of the lower subject [subject] a way for using both mmc and spi mode on a system board HMS30C7202 79 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 79 - 9.3 smc controller this smartmedia? card controller is an advanced microcontroller bus architecture (amba) compliant system-on-a-chip peripheral providing an interface to industry-standard smartmedia? flash memory card. a channel has 8 control signal outputs and 8 bits of bi-directional data ports. features z one 3.3v smartmedia support z 4mb to 128mb media (both flash and mask rom type) z interrupt mode support when eras e/write operation is finished z unique id smartmedia support z multi-page dma access z marginal timing operation settable. 9.3.1 external signals pin name type description smd [7:0] i/o smart media card (ssfdc) 8bit data signals nsmwp o smart media card (ssfdc) write protect nsmwe o smart media card (ssfdc) write enable smale o smart media card (ssfdc) address latch enable smcle o smart media card (ssfdc) command latch enable nsmcd i smart media card (ssfdc) card detection signal nsmce o smart media card (ssfdc) chip enable nsmre o smart media card (ssfdc) read enable nsmrb i smart media card (ssfdc) ready/nbusy signal. this is open-drain output so it requires a pull-up resistor. 9.3.2 registers address name width default description 0x8001.6000 smccmd 32 0x0 smartmedia card command register 0x8001.6004 smcadr 27 0x0 smartmedia card address register 0x8001.6008 smcdatw 32 0x0 data written to smartmedia card 0x8001.600c smcdatr 32 0x0 data received from smartmedia card 0x8001.6010 smcconf 8 0x0 smartmedia card controller configuration register 0x8001.6014 smctime 20 0x0 timing parameter register 0x8001.601c smcstat 32 0x0 smartmedia card controller status register table 9-16 smartmedia controller register summary 9.3.2.1 smc command register (smccmd) 0x8001.6000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hidden command 0 hidden command 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 main command second command bits type function 31:24 r/w hidden command 0. this unique id featur e will be available to 128mb nand flash and upward density products to prevent illegal copy of music files. unique id is put into redundant block of smartmedia. use this hidden command to access redundant block that cannot be accessed with open command, this byte filed is ignored when user block is accessed. for more information, refer to smartmedia maker?s datasheet. 23:16 r/w hidden command 1. read id command returns whether the smartmedia card supports unique id or not. hidden 2 step command for samsung is 30h-65h and for toshiba is 5ah- HMS30C7202 80 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 80 - b5h. to return back to user block after accessing redundant block area, reset command (ffh) should be carried out. 15:8 r/w there are 9 commands to operate smartmedia card. this controller supports only parts of them (bold type). set 1 st command into this byte field except writing to smartmedia. for write operation, set this byte field to serial data input (80h) and set second command byte field to page program (10h). function 1 st cycle 2 nd cycle function 1 st cycle 2 nd cycle serial data input 80h page program 10h read 0 00h block erase 60h d0h read 1 01h status read 70h read 2 50h id read 90h reset ffh 7:0 r/w set 2 nd command here 9.3.2.2 smc address register (smcadr) 0x8001.6004 26 25 24 23 22 21 20 19 18 17 16 smcadr26 ~ smcadr16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smcadr15 ~ smcadr0 bits type function 26:0 r/w smc address. smc controller begins to operate after writing an address to smcadr. hence a valid command must be set to smccmd before writing to smcadr. however, reset and status read commands activate smc controller after writing to smccmd because they do not require an address. following table shows valid address range according to smartmedia card size. model valid page address 4 mb smcadr0 ~ smcadr21 8 mb smcadr0 ~ smcadr22 16 mb smcadr0 ~ smcadr23 32 mb smcadr0 ~ smcadr24 64 mb smcadr0 ~ smcadr25 128 mb smcadr0 ~ smcadr26 9.3.2.3 smc data write register (smcdatw) 0x8001.6008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n * (smcadr + 3)?s byte data n * (smcadr + 2)?s byte data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 n * (smcadr + 1)?s byte data n * smcadr?s byte data bits type function 31:0 r/w four byte data written to this register will be sent to smartmedia. smc controller receives a 32bit data from host controller or dma controlle r. then it starts to transmit from least significant byte to most significant byte, one by te at a time. this smc controller writes a whole page at a single write transaction, so it r equires 132 times consecutive writing (528 = 512+16 bytes). a page program process is as follows: 1. set smccmd to xxxx8010h (sequential data input + page program), smcadr to desired target page address space, and then write first 4 byte data onto smcdatw. if dma mode enabled, dma interrupt will be repeated until it writes 528 byte data to smartmedia. in normal mode, interrupt will be generated every 4 bytes write. 2. at the end of sequential data input, smartmedia goes into page program mode by transmitting the second command to smartmedia. usually page program takes long time, no polling status register is recommended. smc c ontroller automatically generates write finish HMS30C7202 81 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 81 - interrupt when smartmedia comes back to ready mode. 9.3.2.4 smc data read register (smcdatr) 0x8001.600c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n * (smcadr + 3)?s byte data n * (smcadr + 2)?s byte data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 n * (smcadr + 1)?s byte data n * smcadr?s byte data bits type function 31:0 r four byte data read from smartmedia is stored in this register. smc controller receives a byte data from smartmedia and stores it into 4 byte internal buffer to create 32bit data. first read byte data is stored at least significant byte and fourth byte data is stored at most significant byte of buffer. host controller or dma controller read this register to get 4 byte data at a time. this smc controller reads a whole page at a si ngle read transaction, so it requires 132 times consecutive reading. a page r eading process is as follows: 1. set smccmd to xxxx00yyh (xxxx can be unique id if redundant area accessed, yy is don?t care. only 00h command is valid. no 01h or 50h command supported) and then set smcadr to target page address. 2. smc controller will access smartmedia with given command and address. 3. interrupt (or dma interrupt according to interrupt mode setting) will be generated after first four byte read. like writing process, reading process reads a whole 528 byte in a page at a single transaction, so interrupt will be 132 times. against to write operation, there is no read fi nish interrupt because we can count the number of read transfers in software or can get the total access word size from byte count of smcstat. 9.3.2.5 smc configuration register (smcconf) 0x8001.6010 31 6 5 4 3 2 1 0 power enable safe margin smc enable cont page en intr en dma en unique id en big card enable bits type function 31 r/w power on bit. to activate smc controller, set this bit. reset will fall the controller into the deep sleep mode. 30:7 - reserved. keep these bits to zero. 6 r/w safe margin enable bit. in normal mode, chip select signal changes simultaneously with read enable and write enable signals. but when this bi t set, the duration of read and write enable signal applied to smartmedia is reduced by 1 aut omatically. by enabling this, the rising edge of read and write enable signal will be earlier than the rising edge of chip enable, which guarantees latching data safely. 5 r/w smc controller enable bit. reset this bit will make smc controller stay in standby mode. no interrupt generated, no action occurred. 4 r/w continuous page read enable. if this bit set, then multi-page can be accessed in a single command and address setting. usually dma controller accesses multiple pages with a start address and a predefined size. setting dma access size in smctime and enabling this bit will automatically read or write smartmedia with dma mode. 3 r/w interrupt enable. after reading a word or before writing a word, the interrupt bit of smcstat will be set and interrupt will occur if intr en is enabled. if this bit is disabled, software must poll the interrupt flag of smcstat to know the occurrence of an interrupt. after writing a whole page (or pages when cont page en is e nabled) to smartmedia, write finish interrupt will also be generated to notice that the smartmedia complete the write operation successfully. 2 r/w dma enable. if set, all interrupt during read or write data will be sent to dma controller. however, write finish interrupt is a still normal interrupt. to minimize cpu burden and to maximize bus utilization, enabling both interrupt and dma mode together is recommended. 1 r/w redundant page enable. when use smartmedia with unique id and want to access redundant page area, set high. this bit cannot be cleared automatically, so in order to read HMS30C7202 82 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 82 - open page area clear this bit and set a reset command to smccmd. 0 r/w larger than 32mb smartmedia support enable. when using 64mb or 128mb smartmedia, set this bit high. 9.3.2.6 smc timing parameter register (smctime) 0x8001.6014 31 30 29 28 27 26 25 24 22 21 20 19 18 17 16 dma size wait counter byte counter 9 8 2 1 0 high counter low counter bits type function 31:28 r/w multi-page dma size bit. maximum 15 pages are accessible at a time. 0000 = not defined. 0001 = 1 page 0010 = 2 pages ? 1111 = 15 pages 27:24 r/w wait counter maximum limit value. waiting time delay between address latch and write data in page program mode or between address latch and read data in read id mode and read status register is determined by this register. 0000 = 1 bclk width 0001 = 2 bclk width ? 1111 = 16 bclk width 23 - reserved 22:16 r/w should set these bits as 0x7f to access full 512 bytes page at one access command (read or program). 15:10 - r e s e r v e d 9:8 r/w high pulse width value of read enable and write enable signal. the width must satisfy the ac characteristics of smartmedia to guarantee corre ct transfer of data. with safety margin enable, width will be decreased by one. 00 = 1 bclk width (0 bclk with safety margin enable. don?t make this case) 01 = 2 bclk width (1 bclk with safety margin enable) 10 = 3 bclk width (2 bclk with safety margin enable) 11 = 4 bclk width (3 bclk with safety margin enable) 7:3 - reserved 2:0 r/w low pulse width value of read enable and write enable signal. the width must satisfy the ac characteristics of smartmedia to guarantee corre ct transfer of data. with safety margin enable, width will be decreased by one. 000 = 1 bclk width (0 bclk with safety margin enable, don?t make this case) 001 = 2 bclk width (1 bclk with safety margin enable) ? 111 = 8 bclk width (7 bclk with safety margin enable) 9.3.2.7 smc status register (smcstat) 0x8001.601c 31 30 29 28 27 26 25 24 cd intr nsmce smcle smale nsmwe nsmre nsmwp smr/b 23 22 21 20 19 18 17 16 current command/card detect notification 15 14 13 12 11 10 9 8 extra area byte count 7 6 5 4 3 2 1 0 HMS30C7202 83 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 83 - internal state card detect irq drq busy bits type function 31 r card detect interrupt. when card inserted or removed, card detect interrupt will be generated. in the interrupt service routine, look at this bit to identify interrupt type. 30:24 r current status of output signals. 23:16 r current active command. if in card detect interrupt, this byte shows 0xcd. 15 r set when extra area of a page is accessed. 14:8 r current address of a page in word units. 7:4 r shows internal state machine?s state. 3 r set when smc enable and smc card inserted. it will be zero when card removed. 2 r interrupt flag 1 r dma interrupt flag 0 r reset shows smc is in idle mode. set means smc in working mode. HMS30C7202 84 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 84 - 9.4 sound interface the sound control unit (scu) is an interface blo ck to transfer sound data to external speakers. the scu is an interface block used to send data to the external speaker through the internal 8-bit da converter. it can process 44.1/22.05/11.025/8khz sa mpled 8-bit mono or 16-bit stereo sound data. this unit has a 32-bit register to receive sound data from the cpu through dma or interrupt mode. this unit requests the dma or interrupt c ontroller every 32-bit processing time, which depends on the sampling frequency. it has two separate signals for dac that indi cate the direction of data for the stereo sound. either higher or lower byte of 16-bit stereo sound data ca n be played through the left or right speaker by programming the control register. during mono playback, th is unit sends the same data for the left and right channels. there are two test registers. both these registers should be cleared duri ng normal operation. ticclk port is also assigned for production test only. features z sound playback z supports programmable sampling rate z 32-bit internal data register for dma z auto dma request z 8-bit resolution dac control z supports non-overlapping left/right signal for dac z supports test mode 9.4.1 external signals pin name type description adacr o sound dac output for right adacl o sound dac output for left 9.4.2 registers address name width default description 0x8001.3000 scont 8 0x0 control register 0x8001.3004 sdadr 32 0x0 data register table 9-17 sound controller register summary 9.4.2.1 scont 0x8001.3000 - 7 6 5 4 3 2 1 0 reserved mono dma por dac rl samp int bits type function 7 r/w 0 ? stereo 1 ? mono 6* r/w dma request masking bit 0 - masking 1 ? unmasking 5 r/w this bit should be cleared to minimi ze power consumption when not in use. 0 - power down mode 1 - normal mode 4 r/w dac operation enable/disable. during disabled, dac is in power save mode. 0 - dac disable 1 - dac enable 3 r/w when cleared, lower byte data go es to left speaker. (adacl pin) 0 - lower byte data goes to adacl pin 1 - lower byte data goes to adacr pin 2:1 r/w programmable sampling rate HMS30C7202 85 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 85 - 00 - 11.025khz 01 - 22.05khz 10 - 44.1khz 11 - 8khz 0* r/w 0 interrupt request masking bit 0 - masking 1 ? unmasking note those bits marked with an asteri sk should not be enabled simultaneously dur ing normal operation. (the programmer can select only one--either interrupt or dma mode.) 9.4.2.2 sdadr this register can be programmed after setting bit 5 of the scont register. 0x8001.3004 31 30 29 ? 2 1 0 sdadr bits type function 32 r/w sound data this register receives data by dma controller or cpu. this unit processes the lower 16-bit data followed by the higher 16-bit data. after the lower 16-bit is processed, this unit is ready to receive new data and sends a request signal to dm a controller or cpu. in mono mode, the lower byte is processed first followed by the higher byte. HMS30C7202 86 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 86 - 9.5 usb slave interface this section describes the implementa tion-specific options of usb protoc ol for a device controller. it is assumed that the user has knowledge of the usb standar d. this usb device controller (usbd) is chapter 9 (of usb specification) compliant, and supports standard device requests issued by the host. the user should refer to the universal serial bus specification revision 1.1 for a full understanding of the usb protocol and its operation. (the usb specific ation 1.1 can be accessed via the world wide web at: http://www.usb.org ). the usbd is a universal serial bus device controller (slave, not hub or host controller) which supports three endpoints and can operate half-duplex at a baud rate of 12 mbps. endpoint 0,by default is only used to communicate control transactions to configure the usbd after it is reset or physically connected to an active usb host or hub. endpoint 0's responsibilities include connection, address assignm ent, endpoint configuration and bus numeration. the connected host that can get a devic e descriptor stored in usbd?s internal rom via endpoint 0 configures the usbd. the usbd uses two separate 32 x 8 bit fifo to buffer receiving and transmitting data to/from the host. the external pins dedicated to this interface are uvpo, uvp, uvmo, uvm, urcvin, nusboe and ususpend. these signals should be connected to usb transceiver such as pdiusbp11 provided by philip semiconductor. refer to data sheet pdiusbp11). the cp u can access the usbd using interrupt controller, by setting the control register appropriately. this sect ion also defines the interface of usbd and cpu. * notice: don?t use this usb device function with a ls device (like a usb mouse) in a same hub. features z full universal serial bus specification 1.1 compliant. z receiver and transceiver have 32 bytes fifo individually (this supports maximum data packet size of bulk transfer). z internal automatic fifo control logic. (accordi ng to fifo status, the usbd generates interrupt service request signals to the cpu) z supports high-speed usb transfer (12mbps). z there are two endpoint of transmitter and receiver respectively, totally three endpoints including endpoint 0 that has responsibility of the device configuration. z cpu can access the internal usb configuration rom storing the device descriptor for hand-held pc (hpc) by setting the predefined control register bit. z usb protocol and device enumeration is perfo rmed by internal state-machine in the usbd. z the usbd only supports bulk transfer of 4-transfer type supported by usb for data transfer. z endpoint fifo (tx, rx) has the control logi c preventing fifo overrun and under run error. note product id: 7210 vendor id: 05b4 * can be modified reference document - hms30c7210_usbd ownload_v1.3.2guide_with_errata.pdf [location: http://www.hynix.com ?sp-mcu-arm core based-hms30c7 210 reference design kit-miscellany] HMS30C7202 87 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 87 - 9.5.1 block diagram conf igurat ion rom (device descriptor) dev (device interface) endpoint 1 (receive fifo) endpoint 2 (transmit fifo) amba interface sie (serial interface engine) us b transceiver dmac request signal fast apb i/f ausbp ausbn figure 9-1 usb block diagram the usb, figure 9-2: usbd block diagram comprises th e serial interface engine (sie) and device interface (dev). the sie connects to the usb through a bus tran sceiver, and performs nrzi conversion, bit un-stuffing, crc checking, packet decoding and serial to parallel c onversion of the incoming data stream. in outgoing data, it does the reverse, t hat is, parallel to serial of outgoing data stream and packetizing the data, crc generation, bit stuffing and nrzi generation. the dev provides the interface between the sie and the device's endpoint fifo, rom storing the device descriptor. the dev handles the usb protocol, interpreting the incoming tokens and packets and collecting and sending the outgoing data packets and handshakes. the endpoints fifo (rx, tx) give the information of their status (full/ empty) to t he amba interface and amba i/f enable t he cpu to access the fifo's status register and the device descriptor stored in rom. t he amba interface generates a fifo read/write strobe without fifo's errors, based on apb signal timing. in ca se of data transmitting through tx fifo (when usb generates an out token, amba i/f generates interrupt to cpu), the us er should set the transmitting enable bit in the control register. if the error of fifo (rx: overrun, tx: under-run) occurs, the amba i/f cannot generate fifo read/ write. 9.5.2 theory of operation the hynix usb core enables a designer to connect virtually any device requiring incoming or outgoing pc data to the universal serial bus. as illustrated in fi gure 9-2: usbd block diagram, the usb core comprises two parts, the sie and dev. the sie c onnects to the universal serial bus via a bus transceiver. the interface between the sie and the dev is a byte-oriented interfac e that exchanges various types of data packets between two blocks. serial interface engine the sie converts the bit-serial, nrzi encoded and bit-st uffed data stream of the usb into a byte and packet oriented data stream required by the dev. as shown in fi gure 9-3: hynix serial interface engine, it comprises seven blocks: digital phase lock loop, input nrzi dec ode and bit-unstuff, packet decoder, packet encoder, output bit stuff and nrzi encode, c ounters, and the crc g eneration & checking block. each of the blocks is described in the following sections. HMS30C7202 88 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 88 - nrz i decoder (input bit unstuff) nrzi encoder (o utput bit stuff) counter crc generation & checking packet decoder digital phase lock loop usb transceiver packet encoder device in te rfa c e figure 9-2 usb serial interface engine digital phase lock loop the digital phase lock loop module takes the incoming data signals from the usb, synchronizes them to the 48mhz input clock, and then looks for usb data transitions. based on these transitions, the module creates a divide-by -4 clock called the usbclock. data is then output from this module synchronous to the usbclock. input nrzi decode and bit-unstuff the input nrzi decodes and bit-unstuff module extracts the nrzi encoded data from the incoming usb data. transitions on the input serial stream indicate a 0, while no transition indicates a 1. six ones in a row cause the transmitter to insert a 0 to force a transition, theref ore any detected zero bit that occurs after six ones is thrown out. packet decoder the packet decoder module receives incoming data bits and decodes them to detect packet information. it checks that the pid (packet id) is va lid and was sent without error. after decoding the pid, the remainder of the packet is split into the address, endpoint, and crc5 fields, if present. the crc checker is notified to verify the data using the incoming crc5 field. if the packet is a data packet, the data is collected into bytes and passed on with an associated valid bit. table 9-6: supported pid types shows the pid types that are decoded (marked as either receive or both). at the end of the packet, either the packetok or pa cketnotok signal is asserted. packetnotok is asserted if any error condition arose (bad valid bit, bit-stuff, bad pid, wrong le ngth of a field, crc error, etc.). pid type value send/receive pid type value send/receive out 4'b0001 receive data1 4'b1011 both in 4'b1001 receive ack 4'b0010 both sof 4'b1101 receive nak 4'b1010 send setup 4'b0000 receive stall 4'b1110 send data0 4'b0011 both pre 4'b1100 receive table 9-18 usb supported pid types packet encoder the packet encoder creates outgoing packets based on signals from the dev. table 9-6: supported pid types shows the pid types that can be encoded (mark ed as send or both). for each packet type, if the associated signal sends type is received from the dev, the packet is created and sent. upon completion of the packet, packettypesent is asserted to inform the dev of the successful transmission. the packet encoder creates the outgoing pid, gr abs the data from the dev a byte at a ti me, signals the crc generator to create the crc16 across the data field, and then sends the crc16 data. the serial bits are sent to the output bit stuff and nrzi encoder. output bit stuff and nrzi encoder the output bit stuff and nrzi encoder takes the outgoing se rial stream from the packet encoder, inserts stuff bits (a zero is inserted after six consecutive ones ), and then encodes the dat a using the nrzi encoding scheme (zeroes cause a transition, ones leave the output unchanged). HMS30C7202 89 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 89 - counter block the counter block tracks the incoming data stream in order to detect the following conditions: reset, suspend, and turnaround. it also signals to the transmit logic (output nrzi and bit stuff) when the bus is idle so transmission can begin. generation and checking block the generation and checking block checks incoming crc5 and crc16 data fields, and generates crc16 across outgoing data fields. it uses the crc polynomial and remainder specified in the usb specification version 1.1. device interface the dev shown in figure 9-4: device interface wor ks at the packet and byte level to connect a number of endpoints to the sie. it understands the usb protocol for incoming and outgoing packets, so it knows when to grab data and how to correctly respond to incoming packets . a large portion of the dev is devoted to the setup, configuration, and control feat ures of the usb. as shown in figure 9- 4: device interface the dev is divided into three blocks: device controller, device rom, and st art of frame. the three blocks are described in the following sections. device controller ctl s tart o f fram e g en eratio n sof endpoints sie figure 9-3 usb device interface device controller device controller the device controller contains a state machine that understands the usb protocol. the (sie) provides the device controller with the type of packet, address val ue, endpoint value, and data stream for each incoming packet. the device controller then checks to see if the packet is targeted to the device by comparing the address/endpoint values with internal registers that were loaded with address and endpoint values during the usb enumeration process. assuming the address/endpoint is a match, the device controller then interprets the packet. data is passed on to the endpoint for all packets except setup packets, which are handled specially. data toggle bits (data0 and data1 as def ined by the usb spec) are maintained by the device controller. for in data packets (device to host) the de vice controller sends either the maximum number of bytes in a packet or the number of bytes available fr om the endpoint. all packets are acknowledged as per the spec. for setup packets, the incoming data is extracted into the relevant internal fields, and then the appropriate action is carried out. table 9-7: supported set up requests lists the types of setup operations that are supported. setup request value supported setup request value supported get status 0 device, interface, endpoint get configuration 8 device clear feature 1 endpoints only set configuration 9 device set feature 3 not supported get interface 10 not supported set address 5 device set interface 11 not supported get descriptor 6 device synch frame 12 not supported set descriptor 7 not supported table 9-19 usb supported setup requests start of frame the start of frame logic generates a pulse whenever ei ther the incoming start of frame (sof) packet arrives or approximately 1 ms after it the last one arrived. this allows an isochronous endpoint to stay in sync even if the sof packet has been garbled. HMS30C7202 90 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 90 - 9.5.3 endpoint fifos (rx, tx) each endpoint fifo has the specific number of fifo depth according to data transfer rate. in case of maximum packet size for bulk transfer is 32 bytes that is supported in usbd. each fifo generates data ready signals (means fifo not full or fifo not empty) to am ba if. it contains the control logic for transferring 4 bytes at a read/write strobe generated by amba to obtain better efficiency of amba bus. 9.5.4 external signals pin name type description usbp i/o usb transceiver signal for p+ usbn i/o usb transceiver signal for n+ 9.5.5 registers address name width default description 0x8005.1000 gctrl 4 0x0 usb global configuration register 0x8005.1004 epctrl 21 0x0 endpoint control register 0x8005.1008 intmask 10 0x3ff interrupt mask register 0x8005.100c intstat 20 0x0 interrupt status register 0x8005.1010 pwr 4 0x0 power control register 0x8005.1018 devid 32 0x721005b4 device id register 0x8005.101c devclass 32 0x ffffff device class register 0x8005.1020 intclass 32 0x ffffff interface class register 0x8005.1024 setup0 32 - setup device request lower address 0x8005.1028 setup1 32 - setup device request upper address 0x8005.102c endp0rd 32 - endpoint0 read address 0x8005.1030 endp0wt 32 - endpoint0 write address 0x8005.1034 endp1rd 32 - endpoint1 read address 0x8005.1038 endp2wt 32 - endpoint2 write address table 9-20 usb slave interface register summary 9.5.5.1 gctrl 0x8005.1000 31 4 3 2 1 0 reserved transel wback resume dmadis bits type function 3 r/w usb transceiver power-down mode selecti on. when this bit is high, suspend signal of internal usb transceiver is forced to go high immediately. this is for power-down scheme of that transceiver when usb function is not us ed. it is recommended that this value keeps zero while usb normal operation 2 r/w hms30c7210 does not supports write-back clear mode for interrupt status register. this bit must be set to ?0?. 1 r/w this enables remote resume capabilities. when this bit set, usb drives remote resume signaling. should be cleared to stop resume 0 r dma disable bit. hms30c7210 d oes not support dma, so value of this bit (logic 1) is not changeable 9.5.5.2 epctrl 0x8005.1004 31 21 20 19 18 17 16 15 14 13 12 reserved clr2 clr1 clr0 e2txb e2snd e2nk e2st e2en 11 10 9 8 7 4 3 2 1 0 HMS30C7202 91 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 91 - e1rcv e1nk e1st e1en e0txb e0nk e0st e0tr e0en bits type function 20 r/w clear endpoint2 fifo pointer(auto cleared by hardware). 19 r/w clear endpoint1 fifo pointer(auto cleared by hardware). 18 r/w clear endpoint0 fifo pointer(auto cleared by hardware). 17~ 16 r/w usb can transmit non maximum sized packe t. this field contains the residue byte which should be transmitted. 15 r/w this bit enables non maximum sized pack et transfer. after non maximum sized packet transfer, this bit is auto cleared and return to maximum packet size transfer mode. 14 r/w when this bit is set, and endpoint2 is not enabled, usb should send nak handshake 13 r/w when this bit is set, and endpoint2 is not enabled, usb should send stall handshake 12 r/w enable endpoint2 as in endpoint 11 r/w this bit must be zero. so only maximum packet size rx transfer mode is supported. this means rx (host out) data packet size is fixed to 32 bytes only. 10 r/w when this bit is set, and endpoint1 is not enabled, usb should send nak handshake 9 r/w when this bit is set, and endpoint1 is not enabled, usb should send stall handshake 8 r/w enable endpoint1 as out endpoint 7~4 r/w this bit stores the byte count which should be transmitted to host when in token is received (exception :: when this bit is 0, 8 byte are transferred) 3 r/w when this bit is set, and endpoint0 is not enabled, usb should send nak handshake 2 r/w when this bit is set, and endpoint0 is not enabled, usb should send stall handshake 1 r/w when this bit1, endpoint0 is confi gured to in endpoint. (others out endpoint) 0 r/w enable endpoint0 9.5.5.3 intmask 0x8005.1008 31 10 9 8 7 6 5 4 3 2 1 0 reserved e0stl sus reset e2em e1ov e1fu e0em e0ov e0fu set bits type function 9 r/w mask endpoint0 stall interrupt 8 r/w mask suspend interrupt 7 r/w mask usb cable reset interrupt 6 r/w mask endpoint2 empty interrupt 5 r/w mask endpoint1 overrun interrupt (may not be used) 4 r/w mask endpoint1 full interrupt 3 r/w mask endpoint0 empty interrupt 2 r/w mask endpoint0 overrun interrupt (may not be used) 1 r/w mask endpoint0 full interrupt 0 r/w mask endpoint0 setup token received interrupt 9.5.5.4 intstat 0x8005.100c 31 20 19 14 13 0 reserved ep1rxbyte ep0rxbyte 9 8 7 6 5 4 3 2 1 0 e0stl sus reset e2em e1ov e1fu e0em e0ov e0fu set bits type function 19~ 14 r/w currently remained byte in endpoint1 receive fifo which should be read by host 13~ 10 r/w currently remained byte in endpoint0 receive fifo which should be read by host 9 r/w endpoint0 stall interrupt 8 r/w suspend interrupt 7 r/w usb cable reset interrupt 6 r/w endpoint2 empty interrupt HMS30C7202 92 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 92 - 5 r/w endpoint1 overrun interrupt (may not be used) 4 r/w endpoint1 full interrupt 3 r/w endpoint0 empty interrupt 2 r/w endpoint0 overrun interrupt (may not be used) 1 r/w endpoint0 full interrupt 0 r/w endpoint0 setup token received interrupt 9.5.5.5 pwr 0x8005.1010 31 4 3 2 1 0 reserved enbclk swupdate pwrmd bits type function 3 r/w enable bclk to usb fifo block. . 2 r/w usb core power mode update mode, when this bit 1, only software can update usb core power mode. but this bit 0, usb core automatically update its power status according to cable state 1 ~ 0 r/w usb power mode 00 : full power down -> usb core can?t detect any c able activity 01 : power power down -> usb can detect an y cable activity but core doesn?t operate normally 10 : full power operation mode 9.5.5.6 devid 0x8005.1018 bits type function 31:0 r/w usb core can change device id field by writing appropriate device id value to this register 9.5.5.7 devclass 0x8005.101c bits type function 23:0 r/w usb core can change device class field by writing appropriate device id value to this register 9.5.5.8 intclass 0x8005.1020 bits type function 23:0 r/w usb core can change interface class field by writing appropriate device id value to this register - while usb device configuration process, host requests descriptors. this usb block has a hard-wired descriptor rom, but ther e are 3 fields (whole 10 bytes size) user adjustable. [device descriptor] - see usb spec. 1.1 (9.6 standard usb descriptor definitions) for more detail offset (byte) initial valu e description adjustable h00 h12 length h01 h01 device h02 h00 spec version 1.00 h03 h01 spec version h04 hff device class yes h05 hff device sub-class yes h06 hff vendor specific protocol yes h07 h08 max packet size HMS30C7202 93 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 93 - h08 hb4 vendor id yes h09 h05 vendor id (05b4) for hme yes h0a h02 product id yes h0b h72 product id (7210) for hme7210 yes h0c h01 device release # h0d h00 device release # h0e h00 manufacturer index string h0f h00 product index string h10 h00 serial number index string h11 h01 number of configurations * devid register has 32-bit width and it covers vendor id to product id (offset from h08 to h0b): devid [31:24] ? h0b, devid [23:16] ? h0a, devi d [15:8] ? h09, devid [7:0] ? h08 * devclass register has 24-bit width and it covers device class to vendor specific protocol (offset from h04 to h06): devclass [23:16] ? h06, devclass [15:8] ? h05, devclass [7:0] ? h04 [configuration descriptor] offset (byte) initial value description adjustable h00 h09 length of this descriptor h01 h02 configuration (2) h02 h20 total length includes endpoint descriptors h03 h00 total length high byte h04 h01 number of interfaces h05 h01 configuration value for this one h06 h00 configuration - string h07 h80 attributes - bus powered, no wakeup h08 h32 max power - 100 ma is 50 (32 hex) h09 h09 length of the interface descriptor h0a h04 interface (4) h0b h00 zero based index 0f this interface h0c h00 alternate setting value (?) h0d h02 number of endpoints (not counting 0) h0e hff interface class, ff is vendor specific yes h0f hff interface sub-class yes h10 hff interface protocol yes h11 h00 index to string descriptor for this interface h12 h07 length of this endpoint descriptor h13 h05 endpoint (5) h14 h01 endpoint direction (00 is out) and address h15 h02 transfer type ? h02 = bulk h16 h20 max packet size - low : 32 byte h17 h00 max packet size - high h18 h00 polling interval in milliseconds (1 for iso) h19 h07 length of this endpoint descriptor h1a h05 endpoint (5) h1b h82 endpoint direction (80 is in) and address h1c h02 transfer type ? h02 = bulk h1d h20 max packet size - low : 32 byte h1e h00 max packet size - high h1f h00 polling interval in milliseconds (1 for iso) * see usb spec. 1.1 (9.6 standard usb descriptor definitions) for more detail * the descriptor has 4 parts : configuration, in terface, endpoint1, endpoint2 (doubled lines) HMS30C7202 94 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 94 - [string descriptor] offset initial value description adjustable h0 h02 size in bytes h1 h03 string type (3) * this index zero string descriptor means a kind of look up table. as there is no other string descriptor and as there is no further information in this descriptor, usb block does not support strings. (all string index fields are filled with zero) 9.5.5.9 setup0 / setup1 0x8005.1024 / 0x8005.1028 bits type function 31:0 r/w usb core can accept vendor specific pr otocol command using endpoint0. this register contains previously received setup device r equest value (64-bit wide, half in each register) - below is request format from host when configuration. [standard device request format] bmrequesttype brequest wvalue windex wlength byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 when host sends request to usb device, this usb bl ock handles a few requests by sie (serial interface engine). this is the condition of request s which this usb sie can handle. z request type must be standard (b00): see usb spec. 9.3 table 9-2 ?format of setup data? for more detail. offset 0 (bmrequesttype field) d[6:5] (type) ; 00 ? st andard, 01 class, 10 ? vendor, 11 ? reserved. z request must be one of these: get_d escriptor, set_address, set_interface, set_configuration, get_interface, get_configuration and get_status. so for requests other than above, hms30c7210 usb sets 9.5.5.4 intstat [0] and it means host sent setup request that usb sie cannot handle by itself and these 9.5. 5.9 setup0 and 9.5.5. 10 setup1 resister hold device request data (8 bytes : 64 bit described above). this function is to handle standard requests that sie cannot handle and to handle vendor specific requests. * note: 9.5.5.4 intstat [0] bit will not go ?high? in case of setup request if sie can handle that request by itself. 9.5.5.10 endp0rd 0x8005.102c bits type function 31:0 r/w each endpoint 0 fifo read 9.5.5.11 endp0wt 0x8005.1030 bits type function 31:0 r/w each endpoint 0 fifo write 9.5.5.12 endp1rd 0x8005.1034 bits type function 31:0 r/w each endpoint 1 fifo read 9.5.5.13 endp2wt 0x8005.1038 bits type function 31:0 r/w each endpoint 2 fifo write HMS30C7202 95 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 95 - 10 slow amba peripherals 10.1 adc interface controller hms30c7210 has internal adc and adc interface logic fo r analog applications of t ouch panel interface, two 8-bit battery check, and one 8-bit sound sampling. if user doesn?t need these applications or want to use for other functions, there?s a direct adc control register available. features z 5-channel 10-bit adc embedded z 4-sample data per one sampling point of touch panel (use 2 channels, x and y, 10-bit) z main and backup battery check function (use 2 channels, 8-bit resolution) z eight 32-byte sound data buffer (8-word buffer, 8-bit sound data) z manual and auto adc power down mode 10.1.1 external signals pin name type description adin[0] analog input touch panel x-axis signal input adin[1] analog input touch panel y-axis signal input adin[2] analog input main battery value input adin[3] analog input backup battery value input adin[4] analog input sound input 10.1.2 registers address name width default description 0x8002.9000 adccr 0x80 adc control register 0x8002.9004 adctpcr 0x0 touch panel control register 0x8002.9008 adcbacr 0x0 battery check control register 0x8002.900c adcsdcr 0x0 sound data control register 0x8002.9010 adcisr 0x0 adc interrupt status register 0x8002.901c adctdcsr 0x0x tip down control/status register 0x8002.9020 adcdircr adc direct control register 0x8002.9024 adcdirdata adc direct data read register 0x8002.9030 adctpxdr0 touch panel x data register 0 0x8002.9034 adctpxdr1 touch panel x data register 1 0x8002.9038 adctpydr0 touch panel y data register 0 0x8002.903c adctpydr1 touch panel y data register 1 0x8002.9040 adctpxdr2 touch panel x data register 2 0x8002.9044 adctpxdr3 touch panel x data register 3 0x8002.9048 adctpydr2 touch panel y data register 2 0x8002.904c adctpydr3 touch panel y data register 3 0x8002.9050 adcmbdata main battery check data register 0x8002.9054 adcbbdata backup battery check data register 0x8002.9060 adcsdata0 sound data register 0x8002.9064 adcsdata1 sound data register 0x8002.9068 adcsdata2 sound data register 0x8002.906c adcsdata3 sound data register 0x8002.9070 adcsdata4 sound data register 0x8002.9074 adcsdata5 sound data register 0x8002.9078 adcsdata6 sound data register 0x8002.907c adcsdata7 sound data register table 10-1 adc controller register summary HMS30C7202 96 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 96 - 10.1.2.1 adc control register (adccr) user can set adcpd to save power consumption by adc. but adc needs 10-40 ms to self calibrate for normal operation. directc bit can be used for direct accessing from cpu to adc without interface function logic. all direct control signals are describe in adcdi rcr register field. basically adc core converts analog data to digital data continuously in every 16 adc operation-clocks. adc operation clock is ?aclk? (3.6864mhz) called as ?pclk? in slow apb wait bit field select conversion time of adc because in certain case interface logic can read wrong or unstable value from adc. sop bit can be used for one-shot operation to save power. when this bit is set and all adc functions are disabled then interface logic st robe ?power down? signal to adc core. longcal signal selects self-calibration time. initially this bit set as ?0 ? it means short calibration time (about 10 ms). but if first a couple of data were wrong value, user should select long calibration time (about 40 ms). 0x8002.9000 7 6 3 2 1 0 adcpd directc wait sop longcal bits type function 7 r/w adc power down bit. write ?1? to go adc power save mode. this bit blocks the clock to adc, so adc c onsumes no power when this bit is set. but after release this bit, adc need 10 ~ 40 ms ca libration time to normal operation. 6 r/w if this bit was set, cpu access directly adc through dircr and directly read adc result value through dirdata register. 5:4 - reserved 3:2 r/w select adc conversion wait time. it is for capture timing of the data from adc to internal register. 00: no wait (read after 16 cycles, default wait time) 01: 2 clock wait (read after 18 cycles) 10: 4 clock wait (read after 20 cycles) 1 r/w self operate power down bit. when this bit is set, aiostop bit will strobe high when no adc functions are enabled. 0 r/w long calibration time. the default adc calib ration time is 10 ms but when needed adc can be calibrated during 40ms with this bit. short calibration time need 96 cycles of 8 khz oclk or 128 cycles of 11 khz oclk and the long time need 384 cycles of 8 khz or 512 cycl es of 11 khz oclk. oclk is determined from srate bit of adcsdcr. adccr. longcal bit adcscr. srate bit calibration time (the number of oclk cycles) 0 0 96 0 1 128 1 0 383 1 1 511 10.1.2.2 adc touch panel control register (adctpcr) this register control functions re lated with touch panel interface. hms30c7210 supports only external drive for touch panel, so prudent setting of this register is needed. 0x8002.9004 7 6 5 4 3 2 1 0 tpen tintmsk swbypss swinvt inttden sshot trate bits type function 7 r/w touch panel read enable bit. write ?1? to enable touch panel function. 6 r/w touch panel read interrupt mask bit. write ?1? to enable touch panel interrupt. 5 r/w touch panel drive signal bypa ss bit for external drive circuit. you must set this bit to bypass switching signals to external pins such as sw_xp, sw_xn, sw_yp and sw_yn. HMS30C7202 97 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 97 - 4 r/w touch panel drive signal inversion bit. for flexibility 3 r/w internal tip-down detection logic enable bit. you must write ?0? to disable this function. 2 r/w single touch panel read operation. normally, touc h panel date read twice. but this bit is set, touch panel data read once for a point and save power to read touch panel. 1:0 r/w select touch panel date sampling rate. it depends on basic operation clock of adc interface(sound sampling rate). 11: 400 or 550 samples / sec 10: 200 or 275 samples / sec 01: 100 or 138 samples / sec 00: 50 or 69 samples / sec 10.1.2.3 adc battery check control register (adcbacr) this registers controls battery check operation. 0x8002.9008 7 6 3 2 mben mintmsk bben bintmsk bits type function 7 r/w main battery check enable write ?1? to enable four 8-bit battery check data recorded in adcmbdata register 6 r/w main battery check interrupt mask bit write ?1? to enable 5:4 - reserved 3 r/w backup battery check enable write ?1? to enable four 8-bit battery check data recorded in adcbbdata register 2 r/w backup battery check interrupt mask bit write ?1? to enable 1:0 - reserved 10.1.2.4 adc sound control register (adcsdcr) this registers controls sound sampling function. srat e bit control base clock of adc interface logic. 0x8002.900c 7 6 0 snden sintmsk srate bits type function 7 r/w sound date capture enable bit write ?1? to enable 6 r/w sound date interrupt mask bit write ?1? to enable 5:1 - reserved 0 r/w sound date sampling rate selection bit. this bit affects to all sampling rates of touch panel and battery operations. 0: 8 khz sound sampling 1: 11.025 khz sound sampling 8/11khz is derived from aclk (3.6864m hz) called as ?pclk? in slow apb . 10.1.2.5 adc interrupt status register (adcisr) read only valid but write ?1? to clear all interrupt value 0x8002.9010 7 6 5 4 1 0 inttp intmb intbb intsd inttd inttu HMS30C7202 98 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 98 - bits type function 7 r/w touch panel data interrupt. write ?1? here to clear this interrupt. 6 r/w main battery checks interrupt. writ e ?1? here to clear this interrupt. 5 r/w backup battery check interrupt. write ?1? to clear this interrupt. 4 r/w sound data interrupt. it will be generated when all the 8 sound registers are full. write ?1? here to clear this interrupt. 3:2 - reserved 1 r/w tip down interrupt. write ?1? here to clear this interrupt. 0 r/w tip up interrupt. write ?1? here to clear this interrupt. 10.1.2.6 adc tip down control status register (adctdcsr) 0x8002.901c 7 6 5 4 3 1 0 tden tdmsk tuen tumsk tpsel tp_x tp_y bits type function 7 r/w touch panel tip-down detection logic enable write ?1? to enable this function 6 r/w touch panel tip-down interrupt mask bit write ?1? to enable interrupt 5 r/w touch panel tip-up detection enable. when this bit is set, once in every 20 oclk cycles, monitor touch panel status periodically. 4 r/w touch panel tip-up interrupt mask bit. 3 r/w select tip down/up monitoring channel (0:x, 1:y) 2 - reserved 1 r/w x axis tip status monitor bit (read only bit) 0 r/w y axis tip status monitor bit (read only bit) 10.1.2.7 adc direct control register (adcdircr) adc i/f has the direct data read function. when dire ctc bit in adccr register is set high, cpu can access directly a/d converter through this register a nd can read conversion data of a/d converter through dirdata register. 0x8002.9020 7 6 5 4 3 2 1 0 aiostop ach bits type function 7 r/w aiostop bit value to access adc directly 6:5 - reserved 4:0 r/w adc channel selection bits to control adc directly 00001: select channel 0 (touch panel x) 00010: select channel 1 (touch panel y) 00100: select channel 2 (main battery) 01000: select channel 3 (backup battery) 10000: select channel 4 (sound input) 10.1.2.8 adc direct data read register (adcdirdata) register can be used to read data from adc. 0x8002.9024 9 8 7 6 5 4 3 2 1 0 ad data bits type function 9:0 r 10-bit ad conversion data HMS30C7202 99 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 99 - 10.1.2.9 adc 1 st touch panel data register 0x8002.9030 ? 0x8002.903c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 xdata1: adctpxdr0, xdata3: adctpxdr1 ydata1: adctpydr0, ydata3: adctpydr1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xdata0: adctpxdr0, xdata2: adctpxdr1 ydata0: adctpydr0, ydata2: adctpydr1 adctpxdr0: 0x80029030 bits type function 31:26 - r e s e r v e d 25:16 r touch panel x data 10-bit, 2/4 of the first sample cycle (xdata1) 15:10 - r e s e r v e d 9:0 r touch panel x data 10-bit, 1/4 of the first sample cycle (xdata0) adctpxdr1: 0x80029034 bits type function 31:26 - r e s e r v e d 25:16 r touch panel x data 10-bit, 4/4 of the first sample cycle (xdata3) 15:10 - r e s e r v e d 9:0 r touch panel x data 10-bit, 3/4 of the first sample cycle (xdata2) adctpydr0: 0x80029038 bits type function 31:26 - r e s e r v e d 25:16 r touch panel y data 10-bit, 2/4 of the first sample cycle (ydata1) 15:10 - r e s e r v e d 9:0 r touch panel y data 10-bit, 1/4 of the first sample cycle (ydata0) adctpydr1: 0x8002903c bits type function 31:26 - r e s e r v e d 25:16 r touch panel y data 10-bit, 4/4 of the first sample cycle (ydata3) 15:10 - r e s e r v e d 9:0 r touch panel y data 10-bit, 3/4 of the first sample cycle (ydata2) 10.1.2.10 adc 2 nd touch panel data register 0x8002.9040 ? 0x8002.904c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 xdata5: adctpxdr2, xdata7: adctpxdr3 ydata5: adctpydr2, ydata7: adctpydr3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 xdata5: adctpxdr2, xdata6: adctpxdr3 ydata5: adctpydr2, ydata6: adctpydr3 adctpxdr2: 0x80029040 bits type function 31:26 - r e s e r v e d 25:16 r touch panel x data 10-bit, 2/4 of the second sample cycle (xdata5) 15:10 - r e s e r v e d 9:0 r touch panel x data 10-bit, 1/4 of the second sample cycle (xdata4) HMS30C7202 100 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 100 - adctpxdr3: 0x80029044 bits type function 31:26 - r e s e r v e d 25:16 r touch panel x data 10-bit, 4/4 of the second sample cycle (xdata7) 15:10 - r e s e r v e d 9:0 r touch panel x data 10-bit, 3/4 of the second sample cycle (xdata6) adctpydr2: 0x80029048 bits type function 31:26 - r e s e r v e d 25:16 r touch panel y data 10-bit, 2/4 of the second sample cycle (ydata5) 15:10 - r e s e r v e d 9:0 r touch panel y data 10-bit, 1/4 of the second sample cycle (ydata4) adctpydr3: 0x8002904c bits type function 31:26 - r e s e r v e d 25:16 r touch panel y data 10-bit, 4/4 of the second sample cycle (ydata7) 15:10 - r e s e r v e d 9:0 r touch panel y data 10-bit, 3/4 of the second sample cycle (ydata6) 10.1.2.11 adc main battery data register (adcmbdata) 0x8002.9050 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 mbdata3 mbdata2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbdata1 mbdata0 bits type function 31:24 r/w forth main battery check data 23:16 r/w third main battery check data 15:8 r/w second main battery check data 7:0 r/w first main battery check data 10.1.2.12 adc backup battery data register (adcbbdata) 0x8002.9054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bbdata3 bbdata2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bbdata1 bbdata0 bits type function 31:24 r/w forth backup battery check data 23:16 r/w third backup battery check data 15:8 r/w second backup battery check data 7:0 r/w first backup battery check data 10.1.2.13 adc sound data register (adcsdata0 ? adcsdata7) HMS30C7202 has 8-word size sound register so it can contain 32 8-bit sound data. in adc interface logic, there are 8-byte(2-word) tempor al buffer for sound data and every 2-word write into sdata0,1 / sdata2,3 / sdata4,5 / sdata6,7 at a time (at end of every "all 8-byte temporal buffer full" HMS30C7202 101 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 101 - time). so, user has to read in 8 x (one sample period) second for getting valid adcsdata0,1(1st 2-word) after sound interrupt. 0x8002.9060 ? 0x8002.907c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 sdata (n+3) sdata (n+2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sdata (n+1) sdata (n) bits type function 31:24 r / w ( 4 n + 3 ) th sound data. (n = adcsdatan) 23:16 r / w ( 4 n + 2 ) th sound data. (n = adcsdatan) 15:8 r/w (4n+1) th sound data. (n = adcsdatan) 7:0 r/w (4n) th sound data. (n = adcsdatan) HMS30C7202 102 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 102 - 10.2 can interface the controller area network (can) is a serial communi cation protocol that can be efficiently used in distributed real-time control with a very high level of se curity. its domain of application ranges from high-speed networks to low cost multiplex wiring. especially in automotive electronics, engine control units, antilock-break- systems, sensors, anti-skid-systems, etc. can be connected using a can with bitrates up to 1 mbit/s. at the same time it is cost-effecti ve to build into vehicle body electronics, e. g. lamp clusters, electric windows etc. to replace the wiring harness otherwise required. the can used in HMS30C7202 performs communication a ccording to the can protocol version 2.0. the register set of the can can be accessed directly by an arm core via the module inte rface. these register are used to control/configure the ca n core and the message handler and to access the message ram. figure 10-1 typical can network features z supports can protocol version 2.0 part a and b z bit rates up to 1mbit/s z disable automatic retransmission mode for time triggered can application z 32 message objects z each message object has its own identifier mask z programmable fifo mode z maskable interrupt z programmable loop-back mode for self test operation z two 16-bit module interface to the amba apb bus from arm 120 ? 120 ? can bus line ecu1 ecu2 ecu2 canh canl HMS30C7202 can controller d r can transceiver canh canl tx rx 120 ? 120 ? can bus line ecu1 ecu2 ecu2 canh canl HMS30C7202 can controller d r can transceiver canh canl tx rx HMS30C7202 103 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 103 - 10.2.1 block diagram can core message ram register module interface message handler can_tx can_rx can clock reset addr data in data out control interrupt can_wait_b figure 10-2 block diagram of the can can core can protocol controller and rx/tx shift register message ram stores message objects and identifier masks registers all registers used to control a nd to configure the can module message handler the state machine controls the data transfer between th e rx/tx shift register of the can core and the message ram as well as the generation of interrupts according to the programming of the control and configuration registers 10.2.2 register map the register map consists of : ? a set of control, confi guration and status registers ? two cpu interface registers se ts for access to the message ram ? 32 message objects located in the message ram base address of can0 : 0x8002.f000 base address of can1 : 0x8003.0000 address name widt h default description can_base+0x000 cancontrol 16 0x0001 can control register can_base+0x004 canstatus 16 0x0000 can status register can_base+0x008 canerror 16 0x0000 can error counting register can_base+0x00c canbittimreg 16 0x2301 can bit timing register can_base+0x010 canintreg 16 0x0000 can interrupt register HMS30C7202 104 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 104 - can_base+0x014 cantestreg 16 0x0000 * can test register can_base+0x018 canbrpext 16 0x0000 ca n brp extension register can_base+0x01c canenable 16 0x0000 can enable register can_base+0x020 if1comr 16 0x0001 interface1 command request register can_base+0x024 if1comm 16 0x0000 interface1 command mask register can_base+0x028 if1mask1 16 0xffff imteface1 mask1 register can_base+0x02c if1mask2 16 0xffff interface1 mask2 register can_base+0x030 if1arb1 16 0x0000 inte rface1 arbitration1 register can_base+0x034 if1arb2 16 0x0000 inte rface1 arbitration2 register can_base+0x038 if1mcont 16 0x0000 interface1 message control register can_base+0x03c if1dataa1 16 0x0000 interface1 data a1 register can_base+0x040 if1dataa2 16 0x0000 interface1 data a2 register can_base+0x044 if1datab1 16 0x0000 interface1 data b1 register can_base+0x048 if1datab2 16 0x0000 interface1 data b2 register can_base+0x080 if2comr 16 0x0001 interface2 command request register can_base+0x084 if2comm 16 0x0000 interface2 command mask register can_base+0x088 if2mask1 16 0xffff interface2 mask1 register can_base+0x08c if2mask2 16 0xffff interface2 mask2 register can_base+0x090 if2arb1 16 0x0000 inte rface2 arbitration1 register can_base+0x094 if2arb2 16 0x0000 inte rface2 arbitration2 register can_base+0x098 if2mcont 16 0x0000 interface2 message control register can_base+0x09c if2dataa1 16 0x0000 interface2 data a1 register can_base+0x0a0 if2dataa2 16 0x0000 interface2 data a2 register can_base+0x0a4 if2datab1 16 0x0000 interface2 data b1 register can_base+0x0a8 if2datab2 16 0x0000 interface2 data b2 register can_base+0x100 txrqst1 16 0x0000 transmission request 1 can_base+0x104 txrqst2 16 0x0000 transmission request 2 can_base+0x120 newdat1 16 0x0000 new data 1 can_base+0x124 newdat2 16 0x0000 new data 2 can_base+0x140 intpnd1 16 0x0000 interrupt pending 1 can_base+0x144 intpnd2 16 0x0000 interrupt pending 2 can_base+0x160 msgval1 16 0x0000 message validation 1 can_base+0x164 msgval2 16 0x0000 message validation 2 ( * : 0b0000.0000.r000.0000 : r = actual value at pin can_rx) 10.2.3 registers 10.2.3.1 can control register can_base+0x000 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 te s t cce dar reserved eie sie ie init bits type function 7 r/w test mode enable, ?1?: test mode. ?0?: normal mode. 6 r/w configuration change enable ?1?: the cpu has write access to the bi t timing register (while init = ?1?). ?0?: the cpu has no write access to the bit timing register. 5 r/w disable automatic retransmission ?1?: automatic retransmission disabled. ?0?: automatic retransmission of distributed message enabled. 4 - reserved 3 r/w error interrupt enable ?1?: enabled - a change in the boff or ewarn in the status register generates an interrupt. ?0?: disabled ? no error status interrupt will be generated 2 r/w status-change interrupt enable ?1?: enabled - successful completion of a message transfer or a detection of can bus error. HMS30C7202 105 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 105 - ?0?: disabled ? no status change interrupt will be generated 1 r/w module interrupt enable ?1?: enabled ?0?: disabled 0 r/w internal initialization pending ?1?: initialization is started. ?0?: normal operation 10.2.3.2 can status register can_base+0x004 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 boff ewarn epass rxok txok lec bits type function 7 r bus off status ?1?: the can module in busoff status. ?0?: the can module is not busoff 6 r error warning status ?1?: at least one of the error counters in the eml(error management logic) has reached the error warning limit of 96. ?0?: both error counters are below the error warning limit of 96 5 r error passive ?1?: the can core is in the error passive state as defined in the can specification ?0?: the can core is error active 4 r received a message successfully ?1?: since this bit was last reset(to zero) by the arm core, a message has been successfully received(independent of the result of acceptance filtering) ?0?: since the arm core last reset this bit, no message has been successfully received. this bit is never reset by the can core 3 r transmitted a message successfully ?1?: since this bit was last reset(to zero) by the arm core, a message has been successfully transmitted(error free and acknowledged by at least one other node). ?0?: since the arm core last reset this bit, no message has been successfully transmitted. this bit is never reset by the can core 2:0 r last error code (see a can spec ification for more information) ?000? : no error ?001? : stuff error ?010? : form error ?011? : acknowledgment error ?100? : bit1 error ?101? : bit0 error ?110? : crc error (a read access to the status register clears the status interrupt.) 10.2.3.3 can error counting register can_base+0x008 15 14 13 12 11 10 9 8 receive error passive receive error count 7 6 5 4 3 2 1 0 transmit error count bits type function 15 r receive error passive ?1?: the receive error counter has reached t he error passive level as defined in the can specification ?0?: the receive error counter is below the error passive level. 14:8 r receive error count HMS30C7202 106 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 106 - actual state of the receive error counter value : 0 ~ 127 7:0 r transmit error count actual state of the transmit error counter value : 0 ~ 255 10.2.3.4 can bit timing register can_base+0x00c 15 14 13 12 11 10 9 8 reserved tseg2 tseg1 7 6 5 4 3 2 1 0 swj brp bits type function 14:12 wc timing segment 2 the timing segment after the sample point, va lid value for tseg2 are [0?7]. the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 11:8 wc timing segment 1 the timing segment before the sample point, va lid value for tseg1 are [1?15]. the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 7:6 wc (re)synchronous jump width valid values are 0~3. the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 5:0 wc baud rate prescaler the value by which the oscillator frequency is divided for generating the bit time quanta. the bit time is built up from a multiple of this quanta. valid values for the baud rate prescaler are 0~63. the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. (wc: write access only if configuration change enable) 10.2.3.5 can interrupt register can_base+0x010 15 14 13 12 11 10 9 8 intid 15 ? 8 7 6 5 4 3 2 1 0 intid 7 ? 0 bits type function 15:0 r interrupt identifier 0x0000 : no interrupt is pending. 0x0001 ~ 0x0020 : number of message object which caused the interrupt. 0x0021 ~ 0x7fff : unused. 0x8000 : status interrupt. 0x8001 ~ 0xffff : unused. 10.2.3.6 can test register can_base+0x014 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 rx tx1 tx0 loop back silent basic reserved bits type function 7 r receive monitors the actual value of the can_rx pin. 6:5 wt control of can_tx pin ?00? : reset value, can_tx is controlled by the can core. HMS30C7202 107 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 107 - ?01? : sample point can be monitored at can_tx pin. ?10? : can_tx pin drives a dominant(?0?) value. ?11? : can_tx pin drives a recessive(?1?) value. 4 wt loop back mode(receiving its own transmission) ?1? : loop-back mode is enabled. ?0? : loop-back mode is disabled. 3 wt silent mode(never send dominant bits) ?1? : the module is in silent mode. ?0? : normal operation. 2 wt basic mode(message-ram is not available) ?1? : if1 registers are used as transmit buffers and if2 registers are used as receive buffer. ?0? : regular mode. message-ram is used as transmit and receive buffer. (wt: write access only if test mode enabled) 10.2.3.7 can brp extension register can_base+0x018 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved brpe bits type function 3:0 wc baud rate prescaler extension 10.2.3.8 can enable register can_base+0x01c 15 14 13 12 11 10 9 8 reserved 7 6 5 4 3 2 1 0 reserved en bits type function 0 r/w ?1? : can module is enabled (enable the clock ?pclk? and ?bclk?). ?0? : disable. 10.2.3.9 interface x command request register can_base+0x020 / 0x080 15 14 13 12 11 10 9 8 busy reserved 7 6 5 4 3 2 1 0 reserved message number bits type function 15 r/w bus flag (write access only when busy = ?0?) ?1? : set to one when writing to the ifx command request register. ?0? : reset to zero when read/write action has finished. 5:0 r/w message number 1 to 32 a message object in the message ram is selected for data transfer. 33 to 63 not a valid message number. 10.2.3.10 interface x command mask register can_base+0x024 / 0x084 15 14 13 12 11 10 9 8 reserved HMS30C7202 108 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 108 - 7 6 5 4 3 2 1 0 wr/rd mask arb control clrintpnd txrqst/ newdat dataa datab bits type function 7 r/w read/write ?1? : write data from the selected interface registers to the message object addressed by the command request register. ?0? : read data from the message object addressed by the command request register into the selected interface register. 6 r/w access interface x mask bits ?1? : read/write identifier mask + mdir + mxtd. ?0? : mask bits unchanged. 5 r/w access interface x arbitration ?1? : read/write identifier + dir + xtd + msgval. ?0? : arbitration bits unchanged. 4 r/w access interface x message control bits ?1? : read/write control bits. ?0? : control bits unchanged. 3 r/w clear(reset) interface x clear interrupt pending ?1? : clear intpnd bit when reading the message object. ?0? : intpnd bit remains unchanged when reading the message object. 2 r/w access transmission request / new data bit wr/rd = write ?1? : set txrqst bit. ?0? : txrqst bit unchanged. wr/rd = read ?1? : reset newdat bit. ?0? : newdat bit unchanged. 1 r/w access data byte 0~3 ?1? : read/write data byte 0~3. ?0? : data byte 0~3 unchanged. 0 r/w access data byte 4~7 ?1? : read/write data byte 4~7. ?0? : data byte 4~7 unchanged. 10.2.3.11 interface x mask 1 register can_base+0x028 / 0x088 15 14 13 12 11 10 9 8 msk15 msk14 msk13 msk12 msk11 msk10 msk9 msk8 7 6 5 4 3 2 1 0 msk7 msk6 msk5 msk4 msk3 msk2 msk2 msk0 see the explanation of 10.2.3.12 10.2.3.12 interface x mask 2 register can_base+0x02c / 0x08c 15 14 13 12 11 10 9 8 mxtd mdir reserved msk28 msk27 msk26 msk25 msk24 7 6 5 4 3 2 1 0 msk23 msk22 msk21 msk20 msk19 msk18 msk17 msk16 mask28-0 : identifier mask(read/write access) msk28-18 : identifier mask standard message msk28-0 : identifier mask extended message. ?1? : the corresponding identifier bit is used for acceptance filtering. ?0? : the corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. bits type function HMS30C7202 109 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 109 - 15 r/w mask extended identifier ?1? : the extended identifier bit(ide) is used for acceptance filtering. ?0? : the extended identifier bit(ide) has no effect on the acceptance filtering 14 r/w mask message direction ?1? : the message direction bit(rtr) is used for acceptance filtering. ?0? : the message direction bit(rtr) has no effect on the acceptance filtering 10.2.3.13 interface x arbitration 1 register can_base+0x030 / 0x090 15 14 13 12 11 10 9 8 id15 id14 id13 id12 id11 id10 id9 id8 7 6 5 4 3 2 1 0 id7 id6 id5 id4 id3 id2 id1 id0 see the explanation of 10.2.3.14 10.2.3.14 interface x arbitration 2 register can_base+0x034 / 0x094 15 14 13 12 11 10 9 8 msgval xtd dir id28 id27 id26 id25 id24 7 6 5 4 3 2 1 0 id23 id22 id21 id20 id19 id18 id17 id16 id28-0 : identifier message(read/write access) id28-18 : identifier standard message id28-0 : identifier extended message. bits type function 15 r/w message validation ?1? : the message object is configured and should be considered by the message handler. ?0? : the message object is ignored by the message handler. 14 r/w extended identifier ?1? :the extended identifier(19 bit) will be used for this message object. ?0? : the standard identifier(11 bit) will be used for this message object. 13 r/w message direction ?1? : transmit ?0? : receive 10.2.3.15 interface x message control register can_base+0x038 / 0x098 15 14 13 12 11 10 9 8 newdat msglst intpnd umask txie rxie rmten txrqst 7 6 5 4 3 2 1 0 eob reserved dlc(3-0) bits type function 15 r/w new data ?1? : the message handler or the cpu has written new data into the data portion of this message object. ?0? : no new data has been written into the data portion of this message object by the message handler since last time th is flag was cleared by the cpu. 14 r/w message lost(only valid for direction = receive) ?1? : the message handler stored a new message into this object when newdat was still set, the cpu has lost a message. ?0? : no message lost since last time this bit was reset by the cpu. 13 r/w interrupt pending ?1? : this message object has generated an interrupt. ?0? : no interrupt was generated by this message object since last time the cpu has cleared this flag. HMS30C7202 110 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 110 - 12 r/w use identifier mask ?1? : use identifier mask. ?0? : identifier mask ignored. 11 r/w transmit interrupt enable ?1? : an interrupt is generated after a successful transmission of a frame. ?0? : no interrupt is generated after a successful transmission of a frame. 10 r/w receive interrupt enable ?1? : an interrupt is generated after a successful reception of a frame. ?0? : no interrupt is generated after a successful reception of a frame. 9 r/w remote enable ?1? : at the reception of a remote frame, txrqst is set. ?0? : at the reception of a remote frame, txrqst is left unchanged. 8 r/w transmit request ?1? : the transmit of this message ob ject is requested and is not yet done. ?0? : this message object is not waiting for transmission. 7 r/w end of buffer(for normal operation, this bit must be set to one) ?1? : fifo operation ? last message object of fifo buffer. ?0? : fifo operation ? if msgval is set, this message object stores the next message. 3:0 r/w data length code number of data bytes ?0000? : 0 ?0001? : 1 ?0010? : 2 ?0011? : 3 ?0100? : 4 ?0101? : 5 ?0110? : 6 ?0111? : 7 ?1000? : 8 10.2.3.16 interface x data a1 register can_base+0x03c / 0x09c 15 14 13 12 11 10 9 8 data1 7 6 5 4 3 2 1 0 data0 bits type function 15:8 r/w data1 : shift register byte 1 7:0 r/w data0 : shift register byte 0 10.2.3.17 interface x data a2 register can_base+0x040 / 0x0a0 15 14 13 12 11 10 9 8 data3 7 6 5 4 3 2 1 0 data2 bits type function 15:8 r/w data3 : shift register byte 3 7:0 r/w data2 : shift register byte 2 10.2.3.18 interface x data b1 register can_base+0x044 / 0x0a4 15 14 13 12 11 10 9 8 data5 7 6 5 4 3 2 1 0 HMS30C7202 111 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 111 - data4 bits type function 15:8 r/w data5 : shift register byte 5 7:0 r/w data4 : shift register byte 4 10.2.3.19 interface x data b2 register can_base+0x048 / 0x0a8 15 14 13 12 11 10 9 8 data7 7 6 5 4 3 2 1 0 data6 bits type function 15:8 r/w data7 : shift register byte 7 7:0 r/w data6 : shift register byte 6 10.2.3.20 transmission request 1 register can_base+0x100 15 14 13 12 11 10 9 8 txrqst 16 ? 9 7 6 5 4 3 2 1 0 txrqst 8 ? 1 see the explanation of [10.2.3.21] 10.2.3.21 transmission request 2 register can_base+0x104 15 14 13 12 11 10 9 8 txrqst 32 ? 25 7 6 5 4 3 2 1 0 txrqst 24 ? 17 txrqst 32 ?1 : transmission request bits(read-only) ?1? : this transmission of this message object is requested and is not yet done. ?0? : this message object is not waiting for transmission. 10.2.3.22 new data 1 register can_base+0x120 15 14 13 12 11 10 9 8 new data 16 ? 9 7 6 5 4 3 2 1 0 new data 8 ? 1 see the explanation of [10.2.3.23] 10.2.3.23 new data 2 register can_base+0x124 15 14 13 12 11 10 9 8 new data 32 ? 25 7 6 5 4 3 2 1 0 new data 24 ? 17 newdat 32 ? 1 : new data bits(read-only) ?1? : the message handler or the cpu has written new data into the data portion of this message object. ?0? : no new data has been written into the data portion of this message object by the message handler since last time this flag was cleared by the cpu. HMS30C7202 112 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 112 - 10.2.3.24 interrupt pending 1 register can_base+0x140 15 14 13 12 11 10 9 8 intpnd 16 ? 9 7 6 5 4 3 2 1 0 intpnd 8 ? 1 see the explanation of [10.2.3.25] 10.2.3.25 interrupt pending 2 register can_base+0x144 15 14 13 12 11 10 9 8 intpnd 32 ? 25 7 6 5 4 3 2 1 0 intpnd 24 ? 17 intpnd 32 ? 1 : interrupt pending(read-only) ?1? : this message object has generated an interrupt. ?0? : no interrupt was generated by this message object since last time the cpu has cleared this flag. 10.2.3.26 message valid 1 register can_base+0x160 15 14 13 12 11 10 9 8 msgval 16 ? 9 7 6 5 4 3 2 1 0 msgval 8 ? 1 see the explanation of [10.2.3.27] 10.2.3.27 message valid 2 register can_base+0x164 15 14 13 12 11 10 9 8 msgval 32 ? 25 7 6 5 4 3 2 1 0 msgval 24 ? 17 msgval 32 ? 1 : message validation(read-only) ?1? : this message object is configured and should be considered by the message handler. ?0? : this message object is ignored by the message handler. note : can data read/write timing diagram HMS30C7202 113 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 113 - pclk (48mhz) can clk (8mhz) psel / pwrite pwdata (apb data) sync_write registers in can valid data valid data data write into can block - two consecutive write accesses must have a minimum distance of 12 pclk period(2 can clock). pclk (48mhz) can clk (8mhz) psel prdata (apb data) valid data data read from can block - two consecutive read accesses must have a minimum distance of 13 pclk period(2 can clock + 1 pclk). sync_read can_addr valid address - a read access to can module with apb interface must be performed as ? double read ?. note : for more information about can used in HMS30C7202 and its application, please refer ? can user manual of HMS30C7202 for software engineer? published by sp-soc team in hynix semiconductor inc. . HMS30C7202 114 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 114 - 10.3 gpio this document describes the progra mmable input /output module (pio). th is is an amba slave module that connects to the advanced peripheral bus (apb). for mo re information about amba, please refer to the amba specification (arm ihi 0001). the i/o status is not changed during ?sleep mode? or ?deep sleep mode?. 10.3.1 external signals pin name type description kscani [7:0] i/o gpio porta [15:8] kscano [7:0] i/o gpio porta [7:0] portb [11:6] i/o gpio portb [11:6] portb[11:10] : dedicated to the external interrupt of pmu nudcd0 i/o gpio portb [5] nudsr0 i/o gpio portb [4] nurts0 i/o gpio portb [3] nucts0 i/o gpio portb [2] nudtr0 i/o gpio portb [1] nuring0 i/o gpio portb [0] nrcs3 i/o gpio portc [10] nrcs2 i/o gpio portc [9] ndmaack i/o gpio portc [8] ndmareq i/o gpio portc [7] pwm1 i/o gpio portc [6] pwm0 i/o gpio portc [5] ps2ck i/o gpio portc [4] ps2d i/o gpio portc [3] canrx0 i/o gpio portc [2] cantx0 i/o gpio portc [1] timerout i/o gpio portc [0] lblen i/o gpio portd [8] ld [15:8] i/o gpio portd [7:0] ra [24] i/o gpio porte [24] cantx1 i/o gpio porte [23] canrx1 i/o gpio porte [22] mmcclk i/o gpio porte [21] mmccd i/o gpio porte [20] mmcdat i/o gpio porte [19] mmccmd i/o gpio porte [18] nrw3 i/o gpio porte [17] nrw2 i/o gpio porte [16] rd [31:16] i/o gpio porte [15:0] 10.3.2 registers address name width default description 0x8002.3000 adata 16 0x0000 gpio porta data register 0x8002.3004 adir 16 0xffff gpio porta data direction register 0x8002.3008 amask 16 0x0000 gpio porta interrupt mask register 0x8002.300c astat 16 0x0000 gpio porta interrupt status register 0x8002.3010 aedge 16 0x0000 gpio porta edge mode register 0x8002.3014 aclr 16 0x0000 gpio porta clear register 0x8002.3018 apol 16 0x0000 gpio po rta polarity register 0x8002.301c aen 16 0x0000 gpio porta enable register 0x8002.3020 bdata 12 0x000 gpio portb data register 0x8002.3024 bdir 12 0xfff gpio portb data direction register HMS30C7202 115 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 115 - 0x8002.3028 bmask 12 0x000 gpio portb interrupt mask register 0x8002.302c bstat 12 0x000 gpio portb interrupt status register 0x8002.3030 bedge 12 0x000 gpio portb edge moderegister 0x8002.3034 bclr 12 0x000 gpio portb clear register 0x8002.3038 bpol 12 0x000 gpio po rtb polarity register 0x8002.303c ben 6 0x00 gpio portb enable register 0x8002.3040 cdata 11 0x000 gpio portc data register 0x8002.3044 cadir 11 0x7ff gpio portc data direction register 0x8002.3048 cmask 11 0x000 gpio portc interrupt mask register 0x8002.304c cstat 11 0x000 gpio portc interrupt status register 0x8002.3050 cedge 11 0x000 gpio portc edge mode register 0x8002.3054 cclr 11 0x000 gpio portc clear register 0x8002.3058 cpol 11 0x000 gpio portc polarity register 0x8002.305c cen 11 0x000 gpio portc enable register 0x8002.3060 ddata 9 0x000 gpio portd data register 0x8002.3064 ddir 9 0x1ff gpio portd data direction register 0x8002.3068 dmask 9 0x000 gpio portd interrupt mask register 0x8002.306c dstat 9 0x000 gpio portd interrupt status register 0x8002.3070 dedge 9 0x000 gpio portd edge mode register 0x8002.3074 dclr 9 0x000 gpio portd clear register 0x8002.3078 dpol 9 0x000 gpio portd polarity register 0x8002.307c den 9 0x000 gpio portd enable register 0x8002.3080 edata 25 0x0000000 gpio porte data register 0x8002.3084 edir 25 0x1ffffff gpio porte data direction register 0x8002.3088 emask 25 0x0000000 gpio porte interrupt mask register 0x8002.308c estat 25 0x0000000 gpio porte interrupt status register 0x8002.3090 eedge 25 0x0000000 gpio porte edge mode register 0x8002.3094 eclr 25 0x0000000 gpio porte clear register 0x8002.3098 epol 25 0x0000000 gpio po rte polarity register 0x8002.309c een 25 0x0000000 gpio porte enable register 0x8002.30a0 tictmdr 1 0x0 gpio tic test mode register 0x8002.30a4 amulsel 16 0x0000 gpio porta multi-function select register 0x8002.30a8 swap 1 0x0 swap pin configuration register 10.3.2.1 adata 0x8002.3000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 adata, adir, amask, astat, aedge, aclr, apol, aen [15:0] bits type function 16 r/w values written to this register will be output on port [a,b,c,d,e] pins if the corresponding data direction bits are set low (port output). values read from this register reflect the external state of port [a,b,c,d,e] not necessarily the value writ ten to it. all bits are cleared by a system reset. when the pio pin is defined as input, this input can be an interrupt source with register setting. on reads, the data register contains the curr ent status of correspondent port pins, whether they are configured as input or output. writing to a data register only affects the pins that are configured as outputs. all pio input pins c an be used as interrupt source with enabled interrupt mask register bit. these interrupt sources can be selected as active high/low, edge/level trigger mode. 10.3.2.2 adir 0x8002.3004 bits type function 16 r/w bits set in this register will select the corresponding pin in port [a,b,c,d,e] to become an input, clearing a bit sets the pin to output. all bits are set by a system reset. HMS30C7202 116 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 116 - 10.3.2.3 amask 0x8002.3008 bits type function 16 r/w bits set in this register will select the co rresponding pin to become an in terrupt source. all bits are cleared by a system reset. 0 = disable interrupt (default) 1 = enable interrupt 10.3.2.4 astat 0x8002.300c bits type function 16 ro all pio signals can be used as interrupt sour ces according to the settings. each port has the following registers and the interrupt signals to interrupt controller. interrupt controller receives active high, level mode interrupt sources only. but pio block can receive not only active high or active low, but also level or edge mode signals. then it interprets and sends interrupt request to the interrupt controller. all bits can be controlled separately. values in this 16-bit read-only register repr esents that the interrupt requests are pending on corresponding pins. all bits are cleared by a system reset. 0 = no interrupt request 1 = interrupt pending (masked interrupt is always 0) 10.3.2.5 aedge 0x8002.3010 bits type function 16 r/w bits set in this 16-bit read/write regist er will select the corresponding pin to become an edge mode interrupt source. all bits are cleared by a system reset. 0 = level mode (default) 1 = edge mode 10.3.2.6 aclr 0x8002.3014 bits type function 16 wo bits set in this 16-bit write-only register will clear the stored interrupt request of corresponding bit in edge mode. all bits are automatically cleared after written. 0 = no action (default) 1 = clear interrupt source (self reset) 10.3.2.7 apol 0x8002.3018 bits type function 16 r/w bits set in this 16-bit read/write register will select the corresponding pin to become an active low mode interrupt source. all bits are clear ed by a system reset. after accessing this register, the edge mode register shoul d be cleared with the clear register. 0 = active high mode 1 = active low mode 10.3.2.8 gpio port a enable register 15 14 13 12 11 10 9 8 porta15 porta14 porta13 porta12 porta11 porta10 porta9 porta8 7 6 5 4 3 2 1 0 porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 0x8002.301c bits type function 15 r/w gpio port a[15] enable 1: port a[15] 0: kscan0[7] HMS30C7202 117 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 117 - 14 r/w gpio port a[14] enable 1: port a[14] 0: kscan0[6] 13 r/w gpio port a[13] enable 1: port a[13] 0: kscan0[5] 12 r/w gpio port a[12] enable 1: port a[12] 0: kscan0[4] 11 r/w gpio port a[11] enable 1: port a[11] 0: kscan0[3] 10 r/w gpio port a[10] enable 1: port a[10] 0: kscan0[2] 9 r/w gpio port a[9] enable 1: port a[9] 0: kscan0[1] 8 r/w gpio port a[8] enable 1: port a[8] 0: kscan0[0] 7 r/w gpio port a[7] enable 1: port a[7] 0: kscani[7] 6 r/w gpio port a[6] enable 1: port a[6] 0: kscani[6] 5 r/w gpio port a[5] enable 1: port a[5] 0: kscani[5] 4 r/w gpio port a[4] enable 1: port a[4] 0: kscani[4] 3 r/w gpio port a[3] enable 1: port a[3] 0: kscani[3] 2 r/w gpio port a[2] enable 1: port a[2] 0: kscani[2] 1 r/w gpio port a[1] enable 1: port a[1] 0: kscani[1] 0 r/w gpio port a[0] enable 1: port a[0] 0: kscani[0] 10.3.2.9 bdata 0x8002.3020 11 10 9 8 7 6 5 4 3 2 1 0 bdata, bdir, bmask, bstat, bedge, bclr, bpol, ben 10.3.2.10 bdir 0x8002.3024 10.3.2.11 bmask 0x8002.3028 10.3.2.12 bstat 0x8002.302c 10.3.2.13 bedge 0x8002.3030 10.3.2.14 bclk 0x8002.3034 10.3.2.15 bpol 0x8002.3038 10.3.2.16 gpio port b enable register 7 6 5 4 3 2 1 0 reserved portb5 portb4 portb3 portb2 portb1 portb0 0x8002.303c bits type function 5 r/w gpio port b[5] enable 1: port b[5] 0: nudcd 4 r/w gpio port b[4] enable 1: port b[4] 0: nudsr 3 r/w gpio port b[3] enable 1: port b[3] 0: nurts 2 r/w gpio port b[2] enable 1: port b[2] 0: nucts 1 r/w gpio port b[1] enable 1: port b[1] 0: nudtr 0 r/w gpio port b[0] enable 1: port b[0] 0: nuring 10.3.2.17 cdata 0x8002.3040 10 9 8 7 6 5 4 3 2 1 0 cdata, cdir, cmask, cstat, cedge, cclr, cpol, cen 10.3.2.18 cdir 0x8002.3044 HMS30C7202 118 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 118 - 10.3.2.19 cmask 0x8002.3048 10.3.2.20 cbstat 0x8002.304c 10.3.2.21 cedge 0x8002.3050 10.3.2.22 cclk 0x8002.3054 10.3.2.23 cpol 0x8002.3058 10.3.2.24 gpio port c enable register 15 14 13 12 11 10 9 8 reserved portc10 portc9 portc8 7 6 5 4 3 2 1 0 portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 0x8002.305c bits type function 10 r/w gpio port c[10] enable 1: port c[10] 0: nrcs3 9 r/w gpio port c[9] enable 1: port c[9] 0: nrcs2 8 r/w gpio port c[8] enable 1: port c[8] 0: ndmaack 7 r/w gpio port c[7] enable 1: port c[7] 0: ndmareq 6 r/w gpio port c[6] enable 1: port c[6] 0: pwm1 5 r/w gpio port c[5] enable 1: port c[5] 0: pwm0 4 r/w gpio port c[4] enable 1: port c[4] 0: ps2ck 3 r/w gpio port c[3] enable 1: port c[3] 0: ps2d 2 r/w gpio port c[2] enable 1: port c[2] 0: canrx0 1 r/w gpio port c[1] enable 1: port c[1] 0: cantx0 0 r/w gpio port c[0] enable 1: port c[0] 0: timerout 10.3.2.25 ddata 0x8002.3060 8 7 6 5 4 3 2 1 0 ddata, ddir, dmask, dstat, dedge, dclr, dpol, den 10.3.2.26 ddir 0x8002.3064 10.3.2.27 dmask 0x8002.3068 10.3.2.28 dbstat 0x8002.306c 10.3.2.29 dedge 0x8002.3070 10.3.2.30 dclk 0x8002.3074 10.3.2.31 dpol 0x8002.3078 10.3.2.32 gpio port d enable register 15 14 13 12 11 10 9 8 reserved portd8 7 6 5 4 3 2 1 0 portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 HMS30C7202 119 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 119 - 0x8002.307c bits type function 8 r/w gpio port d[8] enable 1: port d[8] 0: lben 7:0 r/w gpio port d[7:0] enable 0xff: port d[7:0] 0x00: ld[15:8] 10.3.2.33 edata 0x8002.3080 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 edata, edir, emask, estat, eedge, eclr, epol, een [24:0] 10.3.2.34 edir 0x8002.3084 10.3.2.35 emask 0x8002.3088 10.3.2.36 ebstat 0x8002.308c 10.3.2.37 eedge 0x8002.3090 10.3.2.38 eclk 0x8002.3094 10.3.2.39 epol 0x8002.3098 10.3.2.40 gpio port e enable register 3 1 30 29 28 27 26 25 24 reserved porte24 23 22 21 20 19 18 17 16 porte23 porte22 porte21 porte20 porte19 porte18 porte17 porte16 15 14 13 12 11 10 9 8 porte15 porte14 porte13 porte12 porte11 porte10 porte9 porte8 7 6 5 4 3 2 1 0 porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 0x8002.309c bits type function 24 r/w gpio port e[24] enable 1:port e[24] 0: ra[24] 23 r/w gpio port e[23] enable 1:port e[23] 0: cantx1 22 r/w gpio port e[22] enable 1:port e[22] 0: canrx1 21 r/w gpio port e[21] enable 1:port e[21] 0: mmcclk 20 r/w gpio port e[20] enable 1:port e[20] 0: mmccd 19 r/w gpio port e[19] enable 1:port e[19] 0: mmcdat 18 r/w gpio port e[18] enable 1:port e[18] 0: mmccmd 17 r/w gpio port e[17] enable 1:port e[17] 0: nrw3 16 r/w gpio port e[16] enable 1:port e[16] 0: nrw2 15:0 r/w gpio port e[15] enable 0xffff : port e[15:0] 0x0000: rd[31:16] 10.3.2.41 tic test mode register(tictmdr) 0x8002.30a0 0 ticsel HMS30C7202 120 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 120 - bits type function 0 r/w when ticsel is high, there is 3 port regi sters (b, d, f) access to check up special word. ticselwr is enabling the tictmdr and pstb is clock signal. so ticsel data output is pd[0] bit. 10.3.2.42 porta multi-function select register(amulsel) 0x8002.30a4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 amulsel bits type function 15 r/w gpio port a[15] multi-function select 1: irin 0: gpio or primary 14 r/w gpio port a[14] multi-function select 1: usout3 0: gpio or primary 13 r/w gpio port a[13] multi-function select 1: usin3 0: gpio or primary 12 r/w gpio port a[12] multi-function select 1: iseck 0: gpio or primary 11 r/w gpio port a[11] multi-function select 1: is ws 0: gpio or primary 10 r/w gpio port a[10] multi-function select 1: port a[10] output 0: gpio or primary 9 r/w gpio port a[9] multi-function select 1: port a[9] output 0: gpio or primary 8 r/w gpio port a[8] multi-function select 1: port a[8] output 0: gpio or primary 7 r/w gpio port a[7] multi-function select 1: irout 0: gpio or primary 6 r/w gpio port a[6] multi-function select 1: usout2 0: gpio or primary 5 r/w gpio port a[5] multi-function select 1: usin2 0: gpio or primary 4 r/w gpio port a[4] multi-function select 1: isclk 0: gpio or primary 3 r/w gpio port a[3] multi-function select 1: isd 0: gpio or primary 2 r/w gpio port a[2] multi-function select 1: port a[2] output 0: gpio or primary 1 r/w gpio port a[1] multi-function select 1: port a[1] output 0: gpio or primary 0 r/w gpio port a[0] multi-function select 1: port a[0] output 0: gpio or primary 10.3.2.43 swap pin configuration register(swap) 0x8002.30a8 0 swap bits type function 0 r/w swap determines port e pin configurati on. when reset, usb transceiver signals, smc and ra24 will be available. otherwise, usb transce iver, smc and can 1 will be available while ra 24 cannot be used so addressing space reduced by half. 10.3.3 gpio interrupt gpio has 7 interrupt sources. each port can be configured as 1 interrupt source except port b. to use a gpio port as interrupt source, specify edge register polarity re gister according to interrupt type, for example, low level sensitive or rising edge sensitiv e, etc. then set mask register to en able interrupt. port b has 3 interrupt sources, portb[11], portb[10] and portb[9:0]. portb[11] is assi gned to make cpu go to deep sleep mode, portb[10] is to detect hotsyn c. portb[9:0] is used as general gpio interrupt source. so, following chart shows available gpio interrupts. interrupt name configurable bits gpioaintr porta[15:0] gpiob0intr portb[10], hotsync interrupt gpiob1intr portb[11], deep sleep interrupt gpiobintr portb[9:0] gpiocintr portc[10:0] gpiodintr portd[8:0] gpioeintr porte[24:0] HMS30C7202 121 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 121 - 10.3.4 gpio rise/fall time data output, unit : ns * it means the drive strength (group a = 1, group b = 2, group c = 4) 50pf 100pf 150pf port number rise fall rise fall rise fall a0~15, b0~11, c0~10, d0~8, e22~23 (*group a) 8.745 10.687 15.946 19.917 23.136 29.147 e0~17,24 (group b) 6.098 5.693 10.896 10.317 15.696 14.927 e18~21 (group c) 4.018 4.048 6.904 7.137 9.783 10.217 HMS30C7202 122 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 122 - 10.4 interrupt controller the HMS30C7202 has a fully programmable priority, indivi dually maskable, vectored interrupt controller. this feature reduces the software overhead in handling interr upts. the interrupt controller can trigger the fast interrupt request (nfiq) and the standard interrupt req uest (nirq) from any interrupt source (on-chip peripherals and gpios). the fully programmable priority enc oder allows the user to define the priority of each interrupt source. external interrupt sources can be positive or negative edge trigger ed or high or low level sensitive, depending on the value programmed in the edge and pol registers (see gpio registers). id code interrupt source id code interrupt source 00 pmu 10 timer1 or timer2 or timer3(64bit) 01 dma 11 watchdog 02 lcd 12 can0 03 sound 13 can1 04 reserved 14 gpiob0 (gpiob [10]) 05 usb 15 gpiob1 (gpiob [11]) 06 mmc 16 gpioa 07 rtc 17 gpiob 08 uart0 18 gpioc 09 uart1 19 gpiod 0a uart2 1a gpioe 0b uart3 1b arm core (commrx debug only) 0c kbd (keyboard interface) 1c arm core (commtx debug only) 0d ps2 1d smartmedia card 0e aic 0f timer0 1e software (auto generation by cpu register set) table 10-2 interrupt controller configuration note the inputs gpiob [10] and gpiob [11] have internally a de- bouncing logic, which allows the direct connection to a button (e.g. for deep sleep and hot sync.). 10.4.1 block diagram interrupt sampling bus i/f apb bridge interrupt source priority control fiq generation irq generation nirq nfiq figure 10-3 interrupt controller block diagram 10.4.2 registers address name width default description 0x8002.4000 ier 31 0x00000000 interrupt enable register 0x8002.4004 isr 31 0x00000000 interrupt status register 0x8002.4008 ivr 32 0x00000000 irq vector register HMS30C7202 123 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 123 - 0x8002.4010 svr0 32 0x00000000 source vector register 0 0x8002.4014 svr1 32 0x00000000 source vector register 1 0x8002.4018 svr2 32 0x00000000 source vector register 2 0x8002.401c svr3 32 0x00000000 source vector register 3 0x8002.4020 svr4 32 0x00000000 source vector register 4 0x8002.4024 svr5 32 0x00000000 source vector register 5 0x8002.4028 svr6 32 0x00000000 source vector register 6 0x8002.402c svr7 32 0x00000000 source vector register 7 0x8002.4030 svr8 32 0x00000000 source vector register 8 0x8002.4034 svr9 32 0x00000000 source vector register 9 0x8002.4038 svr10 32 0x00000000 source vector register 10 0x8002.403c svr11 32 0x00000000 source vector register 11 0x8002.4040 svr12 32 0x00000000 source vector register 12 0x8002.4044 svr13 32 0x00000000 source vector register 13 0x8002.4048 svr14 32 0x00000000 source vector register 14 0x8002.404c svr15 32 0x00000000 source vector register 15 0x8002.4050 svr16 32 0x00000000 source vector register 16 0x8002.4054 svr17 32 0x00000000 source vector register 17 0x8002.4058 svr18 32 0x00000000 source vector register 18 0x8002.405c svr19 32 0x00000000 source vector register 19 0x8002.4060 svr20 32 0x00000000 source vector register 20 0x8002.4064 svr21 32 0x00000000 source vector register 21 0x8002.4068 svr22 32 0x00000000 source vector register 22 0x8002.406c svr23 32 0x00000000 source vector register 23 0x8002.4070 svr24 32 0x00000000 source vector register 24 0x8002.4074 svr25 32 0x00000000 source vector register 25 0x8002.4078 svr26 32 0x00000000 source vector register 26 0x8002.407c svr27 32 0x00000000 source vector register 27 0x8002.4080 svr28 32 0x00000000 source vector register 28 0x8002.4084 svr29 32 0x00000000 source vector register 29 0x8002.4088 svr30 32 0x00000000 source vector register 30 0x8002.4090 idr 32 0x00001f1f interrupt id register 0x8002.4094 psr0 32 0x03020100 priority set register 0 0x8002.4098 psr1 32 0x07060504 priority set register 1 0x8002.409c psr2 32 0x0b0a0908 priority set register 2 0x8002.40a0 psr3 32 0x0f0e0d0c priority set register 3 0x8002.40a4 psr4 32 0x13121110 priority set register 4 0x8002.40a8 psr5 32 0x17161514 priority set register 5 0x8002.40ac psr6 32 0x1b1a1918 priority set register 6 0x8002.40b0 psr7 32 0x001e1d1c priority set register 7 table 10-3 interrupt controller register summary 10.4.2.1 interrupt enable register (ier) this register is used to enable/disable th e interrupt request of interrupt sources. 0x8002.4000 bits type function 31 r/w 0 : enable fiq for priority 0 interrupts , 1 : di sable fiq (a priority 0 interrupt will trigger irq) 30 r/w software interrupt 29 r/w smartmedia card 28 r/w arm core (commtx: debug only) 27 r/w arm core (commrx: debug only) 26 r/w gpio port e 25 r/w gpio port d 24 r/w gpio port c 23 r/w gpio port b 22 r/w gpio port a 21 r/w external interrupt1 (gpiob[11]) 20 r/w external interrupt0 (gpiob[10]) HMS30C7202 124 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 124 - 19 r/w can1 18 r/w can0 17 r/w watchdog timer 16 r/w timer1 or timer2 or timer3(64bit) 15 r/w timer0 14 r/w aic 13 r/w ps2 12 r/w kbd (keyboard interface) 11 r/w uart3 10 r/w uart2 9 r/w uart1 8 r/w uart0 7 r/w rtc 6 r/w mmc 5 r/w usb 4 r/w reserved 3 r/w sound 2 r/w lcd 1 r/w dma 0 r/w pmu note 0: disable interrupt / 1: enable interrupt the interrupt signals of timer 1, 2, and 3 are merged into one interrupt source in timer block. so, you can use these ored signal as one interrupt source. 10.4.2.2 interrupt status register (isr) the irq status register indicates whether or not the interrupt source has triggered an irq interrupt. 0x8002.4004 bits type function 31 r/o reserved 30 r/o software interrupt 29 r/o smartmedia card 28 r/o arm core (commtx: debug only) 27 r/o arm core (commrx: debug only) 26 r/o gpio port e 25 r/o gpio port d 24 r/o gpio port c 23 r/o gpio port b 22 r/o gpio port a 21 r/o external interrupt1 (gpiob[11]) 20 r/o external interrupt0 (gpiob[10]) 19 r/o can1 18 r/o can0 17 r/o watchdog timer 16 r/o timer1 or timer2 or timer3(64bit) 15 r/o timer0 14 r/o aic 13 r/o ps2 12 r/o kbd (keyboard interface) 11 r/o uart3 10 r/o uart2 9 r/o uart1 8 r/o uart0 7 r/o rtc 6 r/o mmc 5 r/o usb 4 r/o reserved 3 r/o sound HMS30C7202 125 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 125 - 2 r/o lcd 1 r/o dma 0 r/o pmu note 0: no interrupt requested (or interrupt source is disabled) 1: interrupt pending 10.4.2.3 irq vector register (ivr) 0x8002.4008 31 ? 0 ivr bits type function 31:0 r the irq vectored register contains the vect or programmed by the user in the source vector register corresponding to the current interrupt. the source vector register (0 to 31) is indexed using the id number in the current interrupt id register when the irq vector register is read. when there is no irq status, the irq vector register is set to 0. 10.4.2.4 source vector register (svr0 to svr30) 0x8002.4010 ~ 0x8002.4088 31 ? 0 ivr bits type function 31:0 r/w the user may store in these register s the address of the corresponding handler for each interrupt source. this interrupt controller has 31-source vector registers, which are corresponded to id code. for example the source vector register of the interrupt by rtc is the svr7 (source vector register 7) 10.4.2.5 interrupt id register (idr) the interrupt id register returns the cu rrent fiq and irq interrupt source number. 0x8002.4090 31 ? 13 12 - 8 7 ? 5 4 - 0 reserved fiqid reserved irqid bits type function 31:13 r reserved 12:8 r fiqid 7:5 r reserved 4:0 r irqid 10.4.2.6 priority set register (psr0 to psr7) the priority set registers consist of 8 registers, repr esenting 32 priority levels. each interrupt source (see table 10-2) has its (unique) priority level. the fiq interr upt source is defined in psr 0[7:0], e.g. if psr0[7:0] = 0x09, uart 1 can trigger the fiq interrupt. 0x8002.4094 ~ 0x8002.40b0 31 ? 24 23 ? 16 15 ? 8 7 ? 0 irq priority * irq priority * irq priority * irq priority * register bits type initial id value function 31:24 r 0x00 reserved 23:16 r/w 0x1e irq priority 1e 15:8 r/w 0x1d irq priority 1d psr7 7:0 r/w 0x1c irq priority 1c 31:24 r/w 0x1b irq priority 1b psr6 23:16 r/w 0x1a irq priority 1a HMS30C7202 126 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 126 - 15:8 r/w 0x19 irq priority 19 7:0 r/w 0x18 irq priority 18 31:24 r/w 0x17 irq priority 17 23:16 r/w 0x16 irq priority 16 15:8 r/w 0x15 irq priority 15 psr5 7:0 r/w 0x14 irq priority 14 31:24 r/w 0x13 irq priority 13 23:16 r/w 0x12 irq priority 12 15:8 r/w 0x11 irq priority 11 psr4 7:0 r/w 0x10 irq priority 10 31:24 r/w 0x0f irq priority f 23:16 r/w 0x0e irq priority e 15:8 r/w 0x0d irq priority d psr3 7:0 r/w 0x0c irq priority c 31:24 r/w 0x0b irq priority b 23:16 r/w 0x0a irq priority a 15:8 r/w 0x09 irq priority 9 psr2 7:0 r/w 0x08 irq priority 8 31:24 r/w 0x07 irq priority 7 23:16 r/w 0x06 irq priority 6 15:8 r/w 0x05 irq priority 5 psr1 7:0 r/w 0x04 irq priority 4 31:24 r/w 0x03 irq priority 3 23:16 r/w 0x02 irq priority 2 15:8 r/w 0x01 irq priority 1 psr0 7:0 r/w 0x00 irq priority 0 or fiq source * note the priority level is to be defined as follows. irq priority 0 or fiq source > irq priority 1 > irq priority 2 > . . . > irq priority 1d> irq priority 1e * disable interrupt type bit( ier bit31) : fiq source / enable interrupt type bit( ier bit31) : irq priority 0 HMS30C7202 127 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 127 - 10.5 matrix keyboard interface controller the matrix keyboard interface controller is an amba slave module that connects to the advanced peripheral bus (apb). for more information about amba, please refer to the amba specification (arm ihi 0001). the interface controller is designed to communicate wi th the external keyboard. the keyboard interface uses the pins kscani [7:0], kscano [7:0]. it is possi ble to select one of four scan clock modes. features z four scanning modes z 8x8 matrix z byte key buffers figure10-4 a flow chart of the keyboard controller 10.5.1 external signals pin name type description kscano [7:0] o this assigns the x-axis' scan li ne. the value is changed periodically so as to cover every key matrix. during one keyboard scan, kscano [7:0] can have 8 different values. active low signal. kscani [7:0] i this indicates which key is pre ssed in the assigned scan line. active low signal 10.5.2 registers address name width default description 0x8002.2000 kbcr 8 0x0 keyboard configuration register 0x8002.2004 kbsc 8 0x0 keyboard scanout register HMS30C7202 128 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 128 - 0x8002.2008 kbtr 8 0x0 keyboard test register 0x8002.200c kbvr0 32 0x0 keyboard value register 0 0x8002.2010 kbvr1 32 0x0 keyboard value register 1 0x8002.2018 kbsr 1 0x0 keyboard status register table 10-4 matrix keyboard interface controller register summary 10.5.2.1 keyboard configuration register (kbcr) 0x8002.2000 7 2 1 0 scan enable npower down clk sel bits type function 7 r/w scanenable bit. this starts or stops matr ix keyboard scanning. to start keyboard input scanning, set the scanenable bit and npowerdown bit of kbcr (keyboard configuration register) and the clk sel bit of the kbcr. the key scan control signal is generated. periodically, column scan code is saved in the 8byte key buffer. after the 8th column key data is stored, keyboard interrupt is generated to make the cpu read 8 scan values. the scanenable bit and npowerdown bit are usually set or reset simultaneously when all the column of keyboard has been scanned, an interrupt is generated, and, by interrogating the kbvr registers, software can determine which keys have been pressed. it is software's responsibilit y to debounce the key pressed information. keyboard key press interrupts are generated in all pmu states except deep sleep. start and stop scanning 0 = stop 1 = start 6:3 - reserved. keep these bits to zero. 2 r/w npowerdown bit. in the power down mode, no clock is inputted to this controller logic. 0 = power down mode, where clock is not operating 1 = normal mode, where clock is operating 1:0 r/w clksel bit. this controls the ope rating clock of scanni ng matrix keyboard. base scanning clock is generated using pclk (3.6864mhz). value base scanning clock rate scan rate (8byte column buffer) 00 pclk/2 (1.84mhz, test mode only) 8861 times/sec 01 pclk/128 (28khz) 138 times/sec 10 pclk/256 (14khz) 69 times/sec 11 pclk/512 (7khz) 34 times/sec 10.5.2.2 keyboard scanout register(kbsc) 0x8002.2004 bits initial function 7 0 0 = 1 st line will be scanned 1 = no scan 6 0 0 = 2 nd line will be scanned 1 = no scan 5 0 0 = 3 rd line will be scanned 1 = no scan 4 0 0 = 4 th line will be scanned 1 = no scan 3 0 0 = 5 th line will be scanned 1 = no scan 2 0 0 = 6 th line will be scanned 1 = no scan 1 0 0 = 7 th line will be scanned 1 = no scan HMS30C7202 129 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 129 - 0 0 0 = 8 th line will be scanned 1 = no scan 10.5.2.3 keyboard test register (kbtr) 0x8002.2008 bits initial function 7 1 indicates whether 1 st key in the selected scan column is pressed 0 = pressed, 1 = not pressed 6 1 indicates whether 2 nd key in the selected scan column is pressed 0 = pressed, 1 = not pressed 5 1 indicates whether 3 rd key in the selected scan column is pressed 0 = pressed, 1 = not pressed 4 1 indicates whether 4 th key in the selected scan column is pressed 0 = pressed, 1 = not pressed 3 1 indicates whether 5 th key in the selected scan column is pressed 0 = pressed, 1 = not pressed 2 1 indicates whether 6 th key in the selected scan column is pressed 0 = pressed, 1 = not pressed 1 1 indicates whether 7 th key in the selected scan column is pressed 0 = pressed, 1 = not pressed 0 1 indicates whether 8 th key in the selected scan column is pressed 0 = pressed, 1 = not pressed 10.5.2.4 keyboard value register (kvr0) 0x8002.200c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1st column kscani [7:0] 2nd column kscani [7:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3rd column kscani [7:0] 4th column kscani [7:0] bits type function 31:24 r 1st column matrix keyboard scan input data. for example, if the value of kbvr0[32:24] is 00001100, the 5th and 6th keys are pressed and the others are released in 1st column. 23:16 r 2nd column matrix keyboard scan input data 15:8 r 3rd column matrix keyboard scan input data 7:0 r 4th column matrix keyboard scan input data 10.5.2.5 keyboard value register (kvr1) 0x8002.2010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5th column kscani [7:0] 6th column kscani [7:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7th column kscani [7:0] 8th column kscani [7:0] bits type function 31:24 r 5th column matrix keyboard scan input data 23:16 r 6th column matrix keyboard scan input data 15:8 r 7th column matrix keyboard scan input data 7:0 r 8th column matrix keyboard scan input data 10.5.2.6 keyboard status register (kbsr) 0x8002.2018 1 0 wakeup intr bits type function HMS30C7202 130 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 130 - 7:2 - reserved 1 r the interrupt and the kbsr bit are cleared after the cpu reads kbsr. the wakeup bit is set if any key is pressed when scanenable bit is inactive. wake up state: 0 = no key pressed or scan enabled 1 = key pressed when scan disabled 0 r key bufferstate: 0 = key buffer is not full 1 = key buffer is full HMS30C7202 131 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 131 - 10.6 ps/2 interface controller this ps/2 controller is an advanced microcontroller bu s architecture (amba) compliant system-on-a-chip peripheral providing industry-standard ps/2 data transfer chann el. a channel has two bi-directional signals that serve as direct interfaces to an external keyboard, mouse or any other ps/2-compatible pointing device. this is an amba slave module that connects to the ad vanced peripheral bus (apb). for more information about amba, please refer to the am ba specification (arm ihi 0001). features z amba compliant z ps/2 compatible interface z half-duplex bi-directional synchronous serial interface using open-drain outputs for clock and data z enable/disable channel z operation in polled or interrupt-driven mode z hardware support for ps/2 auxiliary device protocol z maskable transmit and receive interrupts z automatic odd parity generation and checking z optional software based ps/2 implementation z test interface controller compat ible test registers and test modes 10.6.1 external signals pin name type description psclk i/o ps/2 compatible clock signal pin. pull-up this pad output (open-drain pad used.) psdat i/o ps/2 compatible data signal pin. also pull-up this pad (open-drain). 10.6.2 registers address name width default description 0x8002.c000 psdata 8 00h transmit/receive data register 0x8002.c004 psstat 7 00h internal status register 0x8002.c008 psconf 6 00h configuration register 0x8002.c00c psintr 5 00h interrupt/error status and interrupt ack register 0x8002.c010 pstdlo 8 00h timing parameter register 0x8002.c014 pstpri 8 00h timing parameter register 0x8002.c018 pstxmt 8 00h timing parameter register 0x8002.c020 pstrec 8 00h timing parameter register 0x8002.c024 pstic0 1 test register 0 0x8002.c024 pstic1 8 test register 1 0x8002.c024 pstic2 8 test register 2 0x8002.c024 pstic3 8 test register 3 0x8002.c024 pstic4 8 test register 4 0x8002.c024 pstic5 8 test register 5 0x8002.c03c pspwdn 1 00h power-down configuration register table 10-5 ps/2 controller register summary note: the initial value of registers may be not correct wi th the condition of testi ng environment. above values are based on tic test environment. with external mo del, some registers may have different value. 10.6.2.1 psdata 0x8002.c000 7 6 5 4 3 2 1 0 transmit / receive data bits type function 7:0 r/w after wake up, ps/2 interface waits for one of two events: HMS30C7202 132 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 132 - 1. if data is written to the psdata register, a transmit sequence is initiated and the data is transmitted serially. 2. if data signal is pulled low by the exter nal devices and clock signal?s negative edge is detected, a receive sequence begins and dat a is clocked into psdata register. at the end of transmission, transmit interrupt will occur. by reading psstat status register will reveal the data is transmitted properly. readi ng psstat also de-asserts transmit interrupt request. ps/2 controller usually remains in receive data mode if no data is transmitting. the controller automatically receives data from external de vice and generates receive interrupt. by just reading psdata register the data will be acquir ed and the receive interrupt will be cleared. 10.6.2.2 psstat 0x8002.c004 6 5 4 3 2 1 0 parity data in clk in rx busy rx full tx busy tx empty bits type function 7 - reserved. always zero 6 r/o the parity bit of the last received data byte 5 r/o double synchronized value of the cu rrent psdat being received/transmitted 4 r/o double synchronized value of the cu rrent psclk being received/transmitted 3 r/o this bit indicates that the ps/2 cont roller is currently receiving data or not 2 r/o this bit indicates that the a data is received and ready to be read 1 r/o this bit indicates that the ps/2 cont roller is currently transmitting data or not 0 r/o this bit indicates that the transmit register is empty and ready to transmit 10.6.2.3 psconf 0x8002.c008 6 5 4 3 2 0 lce force dat low force clk low rx intren tx intren enable bits type function 7 - reserved 6 r/w l ine c ontrol detection e nable bit. if set, ps/2 controller checks the line control bit from external device following by stop bit. otherwise ps/2 controller skips checking line control bit and proceeds to next operation. default va lue is zero. most ps/2 compatible device supports line control bit mechanism. but there ar e some devices that don?t support line control bit. to handle such device, ps/2 controller can ski p line control bit detection by resetting this bit. 5 r/w when set, psdat output is forced low regard less of the current state of the ps/2 control logic. this mode can be used as manual communication with external device. 4 r/w when set, psclk output is forced low regardless of the current state of the ps/2 control logic. 3 r/w enable receiver interrupt. to set means enable interrupt. receiver interrupt is generated whenever ps/2 controller finishes receiving a byte data from external device. except when transmit data, ps/2 controller goes in receiv e mode automatically. if receiver interrupt is disabled, ps/2 controller doesn?t notify a data rece ived. so polling psintr interrupt register is needed. 2 r/w enable transmitter interrupt. to set means enable interrupt. transmitter interrupt is generated whenever ps/2 controller completes to transmit a byte data to external device. if transmitter interrupt is disabled then poll status register to know that the transmitting transaction is completed or poll interrupt register transmitter interrupt is generated. 1 - reserved 0 r/w when reset, ps/2 controller is disabled and gets into deep sleep mode. when set, enabled. to activate ps/2 controller,, first set proper para meters of timing registers and then set this bit. as soon as this bit is enabled, ps/2 cont roller goes into receive mode by default. HMS30C7202 133 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 133 - 10.6.2.4 psintr 0x8002.c00c 4 3 2 1 0 transmit timeout receive timieout parity error rx intr tx intr bits type function 7:5 - reserved 4 r/o set when ps/2 controller fails to send a complete byte data to external device in a given time. the time limit is defined in pstxmt register. ps/2 controller doesn?t try to re-transmit the data. reset when psstat register is read. 3 r/o set when a byte data was not constructed in a certain predefined time limit due to no more bit received or bit-rate is too slow. the time lim it is defined in pstrec register. psdata shows the incomplete data that has been received by that time. reset as soon as the next byte data is arrived. 2 r/o set when the last received data has parity error. cleared when the very next byte data is arrived. 1 r/o set when ps/2 controller receives a byte data from external device. cleared when psdata register is read. when psconf.rxintren is reset, the only way to know that receiver interrupt is generated is to read this bit. 0 r/o set when ps/2 controller completes to transmit a byte data to external device. cleared when psstat register is read. when psconf.txintren is reset, poll this bit to confirm that the transmission is completed. 10.6.2.5 pstdlo 0x8002.c010 7 6 5 4 3 2 1 0 pstdlo bits type function 7:0 r/w t pstdlo means the period that defines pclk low period before initiates transmission (a in figure 10-5 ps/2 controller transmitting data timing diagram ). usually the value is 64us. to meet this conditi on, user must set this timing register properly. int(64us/(pclk period) ? 1) is appr opriate value for this register. a: t pstdlo , b: t pstpri , c: t xmt , d: t pstxmt figure 10-5 ps/2 controller transmitting data timing diagram 10.6.2.6 pstpri 0x8002.c014 7 6 5 4 3 2 1 0 pstpri HMS30C7202 134 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 134 - bits type function 7:0 r/w every timer in ps/2 controller is clock ed by priclk except pri counter that generates priclk itself. the reason why uses priclk inst ead of pclk is that pclk is too fast so timing check counter requires more bits than sl ower clock rate. the period of priclk is determined by (pstpri+1) * that of pclk. 10.6.2.7 pstxmt 0x8002.c018 7 6 5 4 3 2 1 0 pstxmt bits type function 7:0 r/w this parameter determines the maxi mum transmission time. it is calculated as t pstxmt (d in figure 10-5 ps/2 controller transmitting data timing diagram ) = (pstxmt+1)*t pstpri (b in figure 10-5 ps/2 controller transmitting data timing diagram ). error condition is when t xmt (total transmission time, c in figure 10-5 ps/2 controller transmitting data timing diagram ) exceeds t pstxmt . typical value of max. t xmt is 15ms. so adjust t pstpri and t pstxmt to meet the condition. 10.6.2.8 pstrec 0x8002.c020 7 6 5 4 3 2 1 0 pstrec bits type function 7:0 r/w this parameter determines the maximum data receiving time. it is calculated as t pstrec (b in figure 10-6 ps/2 controller receiving data timing diagram ) = (pstrec+1)*t pstpri (a in figure 10-6 ps/2 controller receiving data timing diagram ). error condition is when t rec (total receiving time, c in figure 10-6 ps/2 controller receiving data timing diagram ) exceeds t pstrec . typical value of max. t rec is 15ms. so adjust t pstpri and t pstrec to meet the condition. a: t pstpri , b: t pstrec , c: t rec figure 10-6 ps/2 controller receiving data timing diagram HMS30C7202 135 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 135 - 10.6.2.9 pspwdn 0x8002.c03c 0 pspwdn bits type function 7:1 - reserved 0 r/w power down disable. the initial value of power on reset is zero that means the ps/2 controller is in power down mode. to wake up ps/2 controller, set other timing registers then set this bit at last. user can put the ps/2 controller into power down mode by resetting this register at any time. 10.6.3 application notes z use pull up resistors at the psclk and psdat pad output. z for example, in order to set t pstxmt as 15ms, when pclk speed is 3.6864mhz (271.3ns), see the procedure shown below. i. first of all, total transmission time factor, t xmt = (pstxmt+1) * t pstpri . ii. so that equation is expanded as follows: t xmt = ( pstxmt+1) * { (pstpri+1) * t pclk }. iii. when t xmt is 15ms and t pclk is 271.3ns, . ( pstxmt+1) * { (pstpri+1) is 55288. iv. due to both pstxmt and pstpri is only 8-bit register, the values of these two register can hold only up to 256. so if we set (pstpri+1) to 256 then (pstxmt+1) will be 216. v. pstpri = 255 10 = ff 16 vi. pstxmt = 215 10 = d7 16 z you can use the same flow to calculate t pstrec . basically as the root, t pstpri , is common with t pstxmt , the only factor you have to calculate is just pstrec. HMS30C7202 136 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 136 - 10.7 rtc this module is a 32-bit counter clocked by a 32768hz clo ck. this clock needs to be provided by the system, as there is no crystal inside the block. it also cont ains a 32-bit match register that can be programmed to generate an interrupt signal when the time in the rtc matches the specific val ue written to this register (alarm function - rtc event). the rtc has two event outputs, one which is synchronized to pclk, rtcirq, and the second, urtcev synchronized to the 32768hz clock. rtcirq is connected to the system interrupt controller, and urtcev is used by the pmu to provide a system alarm wake up. figure 10-7 rtc connection as shown in fig. 10-3, rtc module is connected to the apb. apb signals are refer to amba apb spec, and following table shows the non-amba signals from the rtc core block. the following table shows non-amba signals within rtc core block for more informat ion about apb signals refer to the amba apb spec. name source/destination description clk32khz clock generator 32768hz clock input. this is the signal that clocks the counter during normal operation. rtcirq apb(interrupt controller) interrupt signal to the interrupt module. when high, this signal indicates a valid comparison between the counter value and the match register. it also indicates 1hz interval with enable bit in control register. urtcev asb(pmu) when high, this signal indicates a valid comparison between the counter value and the match register. this signal is used to wake up the HMS30C7202 when it is in deep sleep mode. table 10-6 non-amba signals within rtc core block features z two type of alarm function HMS30C7202 137 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 137 - 10.7.1 external signals pin name type description rtcoscin i rtc oscillator input. 32.768khz rtcoscout o rtc oscillator output. 32.768khz 10.7.2 functional description the counter is loaded by writing to the rtc data register. the counter will count up on each rising edge of the 1hz clock and loops back to 0 when the maximum value(0xffffffff) is reached. at any moment the counter value can be obtained by reading the rtc data register. the value of the match register can also be read at any time, and the read does not affect the counter value. the status of the interrupt signal is available in the status register. the st atus bit is set if a comparator match event has occurred or 1 second has elapsed. reading from the status register will clear the status register . figure 10-8 rtc block diagram 10.7.3 registers address name width default description 0x8002.8000 rtcdr 32 0x0 rtc data register 0x8002.8004 rtcmr 32 0xf rtc match register 0x8002.8008 rtcs 2 0x0 rtc status register 0x8002.8010 rtccr 2 0x0 rtc control register table 10-7 rtc register summary 10.7.3.1 rtc data register (rtcdr) 0x8002.8000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rtcdr [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rtcdr [15:0] bits type function 31:0 r/w rtc data register. writing to this 32-bit register will load the counter. a read will give the HMS30C7202 138 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 138 - current value of the counter. the counter is l oaded by writing to the rtc data register. the counter will count up on each rising edge of the clock and loops back to 0 when the maximum value (0xffffffff) is reached. at any mo ment the counter value can be obtained by reading the rtc data register. 10.7.3.2 rtc match register (rtcmr) 0x8002.8004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rtcmr [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rtcmr [15:0] bits type function 31:0 r/w rtc match register. if this register?s value is matched with current counter, an interrupt will be generated to implement alarm function. writing to this 32-bit register will load the match register. this value can also be read back. 10.7.3.3 rtc status register (rtcs) 0x8002.8008 1 0 match flag 1 sec flag bits type function 7:2 - reserved 1 r match event interrupt flag is set if the count er value equals to the content of match register, rtcmr. reading from the status regist er will clear the status register. 0 r when performing a read from this register the interrupt flag will be cleared. if 1 second has elapsed, this bit will be set. 10.7.3.4 rtc control register (rtccr) 0x8002.8010 1 0 match intr en 1 sec intr en bits type function 7:2 - reserved 1 r/w set this bit enables match event interrupt. 0 r/w set this bit enables 1 second event interrupt. HMS30C7202 139 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 139 - 10.8 timer this module is a 32-bit counter clocked by a 3.6864mhz clock. timer is an amba slave module that connects to the ad vanced peripheral bus (apb). for more information about amba, please refer to the am ba specification (arm ihi 0001). features z 32-bit up ripple counter z auto repeat mode z count enable/disable z interrupt enable/disable z 3-timer channel 10.8.1 external signals pin name type description pwm [1:0] o pwm output timerout o timer 1 output divided by 2 10.8.2 registers address name width default description 0x8002.5000 t0base 32 0xffffffff timer0 base register 0x8002.5008 t0count 32 0x0 timer0 counter register 0x8002.5010 t0ctrl 3 0x0 timer0 control register 0x8002.5020 t1base 32 0xffffffff timer1 base register 0x8002.5028 t1count 32 0x0 timer1 counter register 0x8002.5030 t1ctrl 3 0x00 timer1 control register 0x8002.5040 t2base 32 0xffffffff timer2 base register 0x8002.5048 t2count 32 0x0 timer2 counter register 0x8002.5050 t2ctrl 3 0x0 timer2 control register 0x8002.5060 topctrl 32 0x9 top-level control register 0x8002.5064 topstat 3 0x0 top-level status register 0x8002.5080 t64low 32 0x0 lower 32-bit of 64-bit counter (timer3) 0x8002.5084 t64high 32 0x0 upper 32-bit of 64-bit counter (timer3) 0x8002.5088 t64ctrl 2 0x0 64-bit time r control register (timer3) 0x8002.508c t64tr 15 0x0 64-bit timer test register (timer3) 0x8002.5094 t64lbase 32 0xffffffff 64-bit timer lower base (timer3) 0x8002.5098 t64hbase 32 0xffffffff 64-bit timer higher base (timer3) 0x8002.50a0 p0count 16 0x0 pwm channel 0 count register 0x8002.50a4 p0width 16 0xffff pwm channel 0 width register 0x8002.50a8 p0period 16 0xffff pw m channel 0 period register 0x8002.50ac p0ctrl 5 0x0 pwm channel 0 control register 0x8002.50b0 p0pwmtr 4 0x0 pwm channel 0 test register 0x8002.50c0 p1count 16 0x0 pwm channel 1 count register 0x8002.50c4 p1width 16 0xffff pwm channel 1 width register 0x8002.50c8 p1period 16 0xffff pw m channel 1 period register 0x8002.50cc p1ctrl 5 0x0 pwm channel 1 control register 0x8002.50d0 p1pwmtr 4 0x0 pwm channel 1 test register table 10-8 timer register summary 10.8.2.1 timer [0,1,2] base register (t[0,1,2]base) 0x8002.5000 / 0x8002.5020 / 0x8002.5040 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HMS30C7202 140 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 140 - t [0,1,2] base [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t [0,1,2] base [15:0] bits type function 31:0 r/w timer 0 (timer 1, timer 2) base register. 32- bit target count value (interval) is stored in here. the interrupt interval in repeat mode is (base register value + 1) clock periods. for example, if the base register is set to 0x3333, then the timer generates an interrupt request every 0x3333 + 1 clock cycles. 10.8.2.2 timer [0,1,2] count register (t[0,1,2]count) 0x8002.5008 / 0x8002.5028 / 0x8002.5048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 t [0,1,2] count [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t [0,1,2] count [15:0] bits type function 31:0 r/w 32bit up counter 10.8.2.3 timer [0,1,2] control register (t[0,1,2]ctrl) 0x8002.5010 / 0x8002.5030 / 0x8002.5050 2 1 0 reset repeat mode count enable bits type function 7:3 - reserved 2 r/w set for reset counter register 1 r/w set for count repeat mode 0 r/w set to start count and reset to stop. for timer 0, timer 1, and timer 2 in non-repeat mode, this bit will be cleared automatically whenever the counter reaches the target value. 10.8.2.4 timer top-level control register (topctrl) 0x8002.5060 6 5 4 3 2 1 0 timer out en timer 64 intr en timer 64 enable power down timer 2 intr en timer 1 intr en timer 0 intr en bits type function 7 - reserved 6 r/w timer 1 output enable. the interval of this out put is 2 times of interrupt interval of timer 1. 0 = disable, 1 = enable 5 r/w 64bit timer counter overflow interrupt enable 0 = disable, 1 = enable 4 r/w 64bit timer enable. 0 = disable, 1 = enable 3 r/w timer controller power down. 0 = power down mode, 1 = enable 2 r/w timer 2 interrupt enable 0 = disable, 1 = enable 1 r/w timer 1 interrupt enable 0 = disable, 1 = enable 0 r/w timer 0 interrupt enable. if reset, no interrupt is generated at timer 0. 0 = disable, 1 = enable HMS30C7202 141 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 141 - 10.8.2.5 timer status register (topstat) 0x8002.5064 3 2 1 0 timer 64 intr timer 2 intr timer 1 intr timer 0 intr bits type function 7:4 - reserved 3 r timer 64 interrupt status flag 2 r timer 2 interrupt status flag 1 r timer 1 interrupt status flag 0 r timer 0 interrupt status flag 10.8.2.6 timer lower 32-bit count register of 64-bit counter (t64low) 0x8002.5080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 t64low [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t64low [15:0] bits type function 31:0 r/w lower 32bit count value of 64bit timer (timer3) 10.8.2.7 timer upper 32-bit count register of 64-bit counter (t64high) 0x8002.5084 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 t64high [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t64high [15:0] bits type function 31:0 r/w upper 32bit count value of 64bit timer (timer3) 10.8.2.8 timer 64-bit counter control register (t64ctrl) 0x8002.5088 2 1 0 reset count enable bits type function 7:3 - reserved 2 r/w reset timer 64 (timer3). 0 = keep counting, 1 = reset the counter register 1 reserved 0 r/w timer 64 (timer3)enable. 0 = stop counter, 1 = start counter 10.8.2.9 timer 64-bit counter test register (t64tr) 0x8002.508c 14 13 12 11 10 9 8 creg59 creg55 creg51 creg47 creg43 creg39 creg35 7 6 5 4 3 2 1 0 creg31 creg27 creg23 creg19 creg15 creg11 creg7 creg3 bits type function HMS30C7202 142 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 142 - 14 w when testreg[59] is high, output is the same as countclk inversion. when testreg[59] is low, output is the same as countreg[59] 13 w when testreg[55] is high, output is the same as countclk inversion. when testreg[55] is low, output is the same as countreg[55] 12 w when testreg[51] is high, output is the same as countclk inversion. when testreg[51]] is low, output is the same as countreg[51] 11 w when testreg[47] is high, output is the same as countclk inversion. when testreg[47] is low, output is the same as countreg[47] 10 w when testreg[43] is high, output is the same as countclk inversion. when testreg[43] is low, output is the same as countreg[43] 9 w when testreg[39] is high, output is the same as countclk inversion. when testreg[39] is low, output is the same as countreg[39] 8 w when testreg[35] is high, output is the same as countclk inversion. when testreg[35] is low, output is the same as countreg[35] 7 w when testreg[31] is high, output is the same as countclk inversion. when testreg[31] is low, output is the same as countreg[31] 6 w when testreg[27] is high, output is the same as countclk inversion. when testreg[27] is low, output is the same as countreg[27] 5 w when testreg[23] is high, output is the same as countclk inversion. when testreg[23] is low, output is the same as countreg[23] 4 w when testreg[19] is high, output is the same as countclk inversion. when testreg[19] is low, output is the same as countreg[19] 3 w when testreg[15] is high, output is the same as countclk inversion. when testreg[15] is low, output is the same as countreg[15] 2 w when testreg[11] is high, output is the same as countclk inversion. when testreg[11] is low, output is the same as countreg[11] 1 w when testreg[7] is high, output is the same as countclk inversion. when testreg[7] is low, output is the same as countreg[7] 0 w when testreg[3] is high, output is the same as countclk inversion. when testreg[3] is low, output is the same as countreg[3] 10.8.2.10 timer lower 32-bit base register of 64-bit counter (t64lbase) 0x8002.5094 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 t64lbase [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t64lbase [15:0] bits type function 31:0 r/w lower 32bit base value of 64bit timer (timer3) 10.8.2.11 timer upper 32-bit base register of 64-bit counter (t64hbase) 0x8002.5098 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 t64hbase [31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t64hbase [15:0] bits type function 31:0 r/w upper 32bit base value of 64bit timer (timer3) 10.8.2.12 pwm channel [0,1] count register (p[0,1]count) 0x8002.50a0 / 0x8002.50c0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p[0,1]count bits type function 15:0 r pwm [0,1] count register HMS30C7202 143 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 143 - 10.8.2.13 pwm channel [0,1] width register (p[0,1]width) 0x8002.50a4 / 0x8002.50c4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p[0,1]width bits type function 15:0 r/w pwm [0,1] width register. actual width of output is (p[0,1]width + 1) / pclk. 10.8.2.14 pwm channel [0,1] period register (p[0,1]period) 0x8002.50a8 / 0x8002.50c8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p[0,1]period bits type function 15:0 r/w pwm [0,1] period register. actual pe riod of output is (p[0,1]period + 1) / pclk. 10.8.2.15 pwm channel [0,1] control register (p[0,1]ctrl) 0x8002.50ac / 0x8002.50cc 4 3 2 1 0 clk sel output invert output enable reset pwm[0,1] enable bits type function 7:5 - reserved 4 r/w pwm [0,1] source clock selection(pclk) 0 = 3.6864mhz, 1 = 1.8432mhz 3 r/w pwm [0,1] output waveform inverting 0 = non inverting, 1 = inverting 2 r/w pwm [0,1] output enable 0 = disable output driver, 1 = enable output driver 1 r/w pwm [0,1] counter reset 0 = keep count, 1 = reset counter register 0 r/w pwm [0,1] counter enable. 0 = stop counter, 1 = start counter 10.8.2.16 pwm channel[0,1] test register(p[0,1]pwmtr) 0x8002.50b0 / 0x8002.50d0 3 2 1 0 reserved creg11 creg7 creg3 bits type function 3 reseved 2 w when testreg[11] is high, output is the same as countclk inversion. when testreg[11] is low, output is the same as countreg[11] 1 w when testreg[7] is high, output is the same as countclk inversion. when testreg[7] is low, output is the same as countreg[7] 0 w when testreg[3] is high, output is the same as countclk inversion. when testreg[3] is low, output is the same as countreg[3] HMS30C7202 144 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 144 - 10.9 uart/sir the 16c550 is a universal asynchronous receiver/transmitter (uart), with fifos, and is functionally identical to the 16c450 on power-up (character mode). the 16550 can be put into an alternate mode (fifo mode) to relieve the cpu of excessive software overhead. in this mode internal fifos are activated, allowing 16 bytes plus 3 bit of error data per byte in the rcvr fifo, to be stored in both receive and transmit modes. all the logic is on the chip to minimize the system overhead and to maximize efficiency. the uart performs serial-to-parallel conversion on dat a characters received from a peripheral device or a modem, and parallel-to-serial conversion on data charac ters received from the cpu. the cpu can read the complete status of the uart at any time during the f unctional operation. status information reported includes the type and condition of the transfer operations being performed by the uart, as well as any error conditions (parity, overrun, framing, or break interrupt). the uart includes a programmable baud rate generator capable of dividing the timing reference clock input by divisors of 1 to 2 16 -1, and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this 16x clock to drive the receiver logic. the uart has complete modem-control capability, an d a processor-interrupt system. interrupts can be programmed to the user's requirement s, minimizing the computing required to handle the communications link. features z capable of running all existing 16c450 software. z after reset, all registers are identical to the 16c450 register set. z the fifo mode transmitter and receiver are each buffered with 16 byte fifos to reduce the number of interrupts presented to the cpu. z add or delete standard asynchronous communication bits (start, stop and parity) to or from the serial data. z holding and shift registers in the 16c450 m ode eliminate the need for precise synchronization between the cpu and serial data. z independently controlled transmit, receiv e, line status and data set interrupts. z programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock z independent receiver clock input. z modem control functions (cts, rts, dsr, dtr, ri and dcd). z fully programmable serial-interface characteristics: - 5-, 6-, 7- or 8-bit characters - even, odd or no-parity bit generation and detection - 1-, 1.5- or 2-stop bit generation and detection - baud generation (dc to 230k baud) z false start bit detection. z complete status-reporting capabilities. z line breaks generation and detection. z internal diagnostic capabilities: - loopback controls for communications link fault isolation z full prioritized interrupt system controls. 10.9.1 external signals pin name type description nuring i uart 0 ring input si gnal (wake-up signal to pmu). when low, this indicates that the mode m or data set has received a telephone ring signal. the nuring signal is a mode m status input whose condition can be tested by the cpu reading bit 6 (ri) of the modem status register. bit 6 is the complement of the nuring signal. bit 2 (teri) of the modem status register indicates whether the nuring input si gnal has changed from a low to a high state since the previous reading of the modem status register. note : whenever the ri bit of the modem status register changes from a high to a low state, an interrupt is generated if the modem status interrupt is enabled. the nuring input from the extern al pad is not provided. to use this signal, you should set up the uart control register of the afe interface. for further information, refer to 13.9 analog front end, afe (codec interface) on HMS30C7202 145 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 145 - page 13-56. nudtr o uart 0 data terminal ready. when low, this informs the modem or data set that the uart is ready to establish communication link. the nudtr output signal can be set to an active low by programming bit 0 (dtr) of the modem control register to high level. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. nucts i uart 0 clear to send input. when low, this indicates that the modem or data set is ready to exchange data. the nu cts signal is a modem status input whose conditions can be tested by the cp u reading bit 4 (cts) of the modem status register indicates whether t he nucts input has changed state since the previous reading of the modem status register. nucts has no effect on the transmitter. note : whenever the cts bit of the modem status register changes its state, an interrupt is generated if the modem status interrupt is enabled. nurts o uart 0 request to send. when low, this informs the modem or data set that the uart is ready to exchange data. the nurts output signal can be set to an active low by programming bit 1 (rts) of the modem control register. a master reset operation sets this signal to its inactive (high) state. loop mode operation holds this signal in its inactive state. nudsr i uart 0 data set ready input. when low, this indicates that the modem or data set is ready to establish the communica tions link with the uart. the nudsr signal is a modem status input whos e conditions can be tested by the cpu reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the nudsr signal. bit 1(ddsr) of modem status register indicates whether the nudsr input has changed state sinc e the previous reading of the modem status register. note : whenever the dsr bit of the modem status register changes its state, an interrupt is generated if the modem status interrupt is enabled. nudcd i uart 0 data carrier detect input. when low, indicates that the data carrier has been detected by the modem data set. t he signal is a modem status input whose condition can be tested by the cp u reading bit 7 (dcd) of the modem status register. bit 7 is the complement of the signal. bit 3 (ddcd) of the modem status register indicates whether the input has changed state since the previous reading of the modem status register. nudcd has no effect on the receiver. note : whenever the dcd bit of the modem status register changes its state, an interrupt is generated if the modem status interrupt is enabled. usin [0] i uart 0 serial data inputs. seri al data input from the communications link (peripheral device, modem or data set). usout [0] o uart 0 serial data outputs. com posite serial data output to the communications link (peripheral, modem or data set). t he usout signal is set to the marking (logic 1) state upon a master reset operation. usin [1] i uart 1 serial data inputs usout [1] o uart 1 serial data outputs usin [2] i uart 2 serial data inputs (muxed with kscano5) usout [2] o uart 2 serial data outputs (muxed with kscano6) usin [3] i uart 3 serial data inputs (muxed with kscani5) usout [3] o uart 3 serial data outputs (muxed with kscani6) 10.9.2 registers address name width default description 0x8002.0000 u0base - - uart 0 base 0x8002.1000 u1base - - uart 1 base 0x8002.d000 u2base - - uart 2 base 0x8002.e000 u3base - - uart 3 base uxbase+0x00 rbr thr 8 0x0 receiver buffer register (dlab = 0, read) transmitter holding register (dlab = 0, write) HMS30C7202 146 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 146 - dll divisor latch least significant byte (dlab = 1) uxbase+0x04 ier dlm 8 0x0 interrupt enable register (dlab = 0) divisor latch most significant byte (dlab = 1) uxbase+0x08 iir fcr 8 0x1 0x0 interrupt identification register (read) fifo control register (write) uxbase+0x0c lcr 8 0x0 line control register uxbase+0x10 mcr 3 0x0 modem control register uxbase+0x14 lsr 8 0x60 line status register uxbase+0x18 msr 8 0xx0 modem status register uxbase+0x1c scr 8 0x0 scratch register uxbase+0x30 uarten 1 or 4 0x0 uart enable register in uart 1, this bit width is 4 (support sir) table 10-9 uart/sir register summary 10.9.2.1 rbr/thr/dll uxbase+0x00 7 6 5 4 3 2 1 0 data bit 7 ~ data bit 0 (rbr, thr; dlab = 0) bit 7 ~ bit 0 (dll; dlab = 1) bits type function 7:0 r/w when dlab = 0, read this register represents rbr while writes does thr. when dlab = 1, dll will be read or written. 10.9.2.2 ier/dlm this register enables the five types of uart interrupts. each interrupt can individually activate the interrupt (intuart) output signal. it is possible to totally disable the interrupt enable register (ier). similarly, setting bits of the ier register to logic 1 enables the selected interrupt(s). disabl ing an interrupt prevents it from being indicated as active in the iir and from activating the intuart output signal. all other system functions operate in their normal manner, including the setting of the line status and modem st atus registers. table 13-6: summary of registers on page 13-10 shows the contents of the ier. details on each bit follow. uxbase+0x04 7 6 5 4 3 2 1 0 0 0 0 0 ms intr ls intr tx empty intr data rdy intr bit 7 ~ bit 0 dlm; (dlab = 1) function bits type ier dlm 7 r/w 0 6 r/w 0 5 r/w 0 4 r/w 0 3 r/w enables the modem status interrupt when set to logic 1. 2 r/w enables the receiver line status interrupt when set to logic 1. 1 r/w enables the transmitter holding register empty interrupt when set to logic 1. 0 r/w enables the received data available interrupt (and time-out interrupts in the fifo mode) when set to logic 1. most significant byte of divisor latch 10.9.2.3 iir/fcr uxbase+0x08 7 6 5 4 3 2 1 0 HMS30C7202 147 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 147 - fifo en 0 0 intr id intr pend rcvr trig level - - - xmit reset rcvr reset fifo en interrupt identification register in order to provide minimum software overhead during data character transfers, the uart prioritizes interrupts into four levels and records these in t he interrupt identification r egister. the four levels of interrupt conditions are, in order of priority 1. receiver line status 2. received data ready 3. transmitter holding register empty 4. modem status when the cpu accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this cpu access is occu rring, the uart records new interrupts, but does not change its current indication until the access is complete. bits type function 7:6 r these two bits are set when fcr [0] = 1. 5:4 r these two bits of the iir are always logic 0 3:1 r these two bits of the iir are used to ident ify the highest priority interrupt pending. in the 16c450 mode, iir [3] is 0. in the fifo mode, iir [3] is set along with iir [2] when a time-out interrupt is pending iir [3:1] interrupt set and reset function priority level interrupt type interrupt source interrupt reset control 000 - none none - 011 highest receiver line status overrun error or parity error or framing error or break interrupt reading the line status register 010 second receiver data available receiver data available or trigger level reached reading the receiver buffer register or the fifo drops below the trigger level 110 second character time-out indication no characters have been removed from or i nput to the rcvr fifo during the last 4 character times and there is at least 1 character in it during this time reading the receiver buffer register HMS30C7202 148 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 148 - 001 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing into the transmitter holding register 000 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register 0 r this bit can be used in a prioritized interrupt environment to indicate whether an interrupt is pending. when bit 0 is logic 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service r outine. when bit 0 is logic 1, no interrupt is pending fifo control register this is a write-only register at the same location as the iir (the iir is a read-only register). this register is used to enable the fifos, clear the fifo s and set the rcvr fifo trigger level. bits type function 7:6 w these two bits sets the trigger level for the rcvr fifo interrupt value rcvr fifo trigger level (bytes) 00 01 01 04 10 08 11 14 5:3 - reserved 2 w writing 1 resets the transmitter fifo counter logi c to 0. the shift register is not cleared. the 1 that is written to this bi t position is self-clearing 1 w writing 1 resets the receiver fifo counter logi c to 0. the shift register is not cleared. the 1 that is written to this bi t position is self-clearing 0 w writing 1 enables both the xmit and rcvr fifos. resetting fcr0 will clear all bytes in both fifos. when changing from fifo mode to 16c450 mode and vice versa, data is automatically cleared from the fifos. this bit must be a 1 when other fcr bits are written to or they will not be programmed 10.9.2.4 lcr the system programmer specifies the format of the as ynchronous data communications exchange and set the divisor latch access bit via the line control register (lcr). the programmer can also read the contents of the line control register. the read capability simpli fies system programming and eliminates the need for separate storage in system memo ry of the line characteristics. uxbase+0x0c 7 6 5 4 3 2 1 0 dlab set break stick parity even parity parity enable stopbit number word length select bits type function 7 this bit is the divisor latch access bit (dlab). it must be set high (logic 1) to access the divisor latches of the baud generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmitter holding register or the interrupt enable register 6 this bit is the break control bit. it causes a break condition to be trans mitted to the receiving HMS30C7202 149 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 149 - uart. when it is set to logic 1, the serial out put (sout) is forced to the spacing (logic 0) state. the break is disabled by setting logic 0. the break control bit acts only on sout and has no effect on the transmitter logic. note: this feature enables the cpu to alert a terminal in a computer communications system. if the following sequence is followed, no erroneous or extraneous characters will be tran smitted because of the break. 5 this bit is the stick parity bit. when bits 3, 4 and 5 are logic 1 the parity bit is transmitted and checked as logic 0. if bits 3 and 5 are 1 and bit 4 is logic 0 then the parity bit is transmitted and checked as logic 1. if bit 5 is a logic 0 stick parity is disabled. 4 this bit is the even parity select bit. when bi t 3 is logic 1 and bit 4 is logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and parity bit. when bit 3 is logic 1 and bit 4 is logic 1, an even number of logic 1s is transmitted or checked. 3 this bit is the parity enable bit. when bit 3 is logic 1, a pari ty bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd num ber of 1s when the data word bits and the parity bit are summed). 2 this bit specifies the number of stop bits tr ansmitted and received in each serial character. if bit 2 is logic 0, one stop bit is generated in the transmitted data. if bit 2 is logic 1 when a 5-bit word length is selected via bits 0 and 1, one an d a half stop bits are generated. if bit 2 is a logic 1 when either a 6-, 7- or 8-bit word l ength is selected, two stop bits are generated. the receiver checks the first stop-bit only, regardless of the number of stop bits selected. 1:0 r/w these two bits specify the number of bits in each transmitted and rece ived serial character. the encoding of bits 0 and 1 is as follows: value character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits programmable baud generator the uart contains a programmable ba ud generator that is capable of taking any clock input from dc to 8.0mhz and dividing it by any divisor from 2 to 2 16 -1. 5.185 mhz(70mhz cpu clock) is the highest input clock frequency recommended when the divisor=1. the output frequency of the baud generator is 16 x the baud [divisor # = (frequency input) / (baud rate x 16)]. two 8- bit latches store the divisor in a 16-bit binary format. these divisor latches must be loa ded during initialization to ensure pr oper operation of t he baud generator. upon loading either of the div isor latches, a 16-bit baud counter is immediately loaded. baud rate table below provides decimal divisors to us e with a crystal frequency of 3.6864mhz. for baud rates of 38400 and below, the error obtained is minimal. the accuracy of the desired baud rate is dependent on the crystal frequency chosen. using a divisor of zero is not recommended. desired baud rate decimal divisor (used to generate 16 x clock) percent error difference between desired and actual 50 4608 - 110 2094 0.026 300 768 - 1200 192 - 2400 96 - 4800 48 - 9600 24 - 19200 12 - 38400 6 - 57600 4 115200 2 table 10-10 baud rate with decimal divisor at 3.6864mhz crystal frequency 10.9.2.5 mcr this register controls the interface with the modem or data set (or a peripheral device emulating a modem). HMS30C7202 150 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 150 - uxbase+0x10 7 6 5 4 3 2 1 0 0 0 0 loop - - rts dtr bits type function 7:5 r these bits are permanently set to logic 0 4 this bit provides a local loop back feature fo r diagnostic testing of the uart. when bit 4 is set to logic 1, the following occur: the transmitter serial output (sout) is set to the marking (logic 1) state; the receiver serial input (s in) is disconnected; the output of the transmitter shift register is "looped back" into the receiver shift register input; the four modem control inputs (ncts, ndsr, ndcd and nri) are disconnected; and the two modem control outputs (ndtr and nrts) are internally connected to the four modem control inputs, and the modem control output pins are forced to th eir inactive state (h igh). on the diagnostic mode, data that is transmitted is immediately re ceived. this feature allows the processor to verify the transmit- and received-data paths of the uart. in the diagnostic mode, the receiver and trans mitter interrupts are fully operational. their sources are external to the pa rt. the modem control interrupts are also operational, but the interrupts sources are now the lower four bits of the modem control register instead of the four modem control inputs. the interrupts are still controlled by the interrupt enable register. 3:2 - reserved 1 this bit controls the request to send (nurts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. 0 r/w this bit controls the data terminal ready (nudtr) output. when bit is set to logic 1, the ndtr output is forced to logic 0. when bit 0 is reset to logic 0, the ndtr output is forced to logic 1. note : the ndtr output of the uart may be applied to an eia inverting line driver (such as the ds1488) to obtain the proper polarity input at the succeeding modem or data set. 10.9.2.6 lsr this register provides status informati on to the cpu concerning the data transfer. uxbase+0x14 7 6 5 4 3 2 1 0 fifo err temt thre bi fe pe oe dr bits type function 7 r in the 16c450 mode this is always 0. in the fifo mode lsr7 is set when there is at least one parity error, framing error or break indica tion in the fifo. lsr7 is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. 6 r this bit is the transmitter empty (temt) indi cator. bit 6 is set to a logic 1 whenever the transmitter holding register (thr) and the transmitter shift register (tsr) are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the tr ansmitter fifo and register are both empty. 5 r this bit is the transmitter holding register empty (thre) indicator. bit 5 indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the cpu when the transmit holding register empty interrupt enable is set high. the thre bit is set to a l ogic 1 when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter ho lding register. in the fifo mode this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo. 4 r this bit is the break interrupt (bi) indicator. bit 4 is set to logic 1 whenever the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). the bi indicator is reset whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. when break occurs, only one zero character is loaded into the fifo. the ne xt character transfer is enabled after sin goes HMS30C7202 151 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 151 - to the marking state and receives the next valid start bit. note : bits 1--4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are det ected and the interrupt is enabled. 3 r this bit is the framing error (fe) indicator. bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to logic 1 whenever the stop bit following the last data bit or parity bit is detected as a logic 0 bit (spacing level). the fe indicator is reset whenever the cpu reads the contents of the line status register . in the fifo mode this error is associated with the particular character in the fifo it app lies to. this error is revealed to the cpu when its associated character is at the top of the fi fo. the uart will try to re-synchronize after a framing error. to do this it assumes that the framing error was due to the next start bit, so it samples this "start" bit twice and then takes in the "data". 2 r this bit is the parity error (pe) indicator. bit 2 indicates that the received data character does not have the correct even or odd parity, as sele cted by the even-parity-s elect bit. the pe bit is set to logic 1 upon detection of a parity error and is reset to logic 0 whenever the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo it applies to . this error is revealed to the cpu when its associated character is at the top of the fifo. 1 r this bit is the overrun error (oe) indicator. bit 1 indicates that data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver buffer register, thereby destroying the previous character. the oe indicator is set to logic 1 upon detection of an overrun condition and reset wh enever the cpu reads the contents of the line status register. if the fifo mode data continues to fill the fifo beyond the trigger level, an overrun error will occur only after the fi fo is full and the next character has been completely received in the shift register. oe is indicated to the cpu as soon as it happens. the character in the shift register is overwr itten, but it is not transferred to the fifo. 0 r this bit is the receiver data ready (dr) indi cator. bit 0 is set to logic 1 whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to logic 0 by reading all of the data in the receiver buffer register or the fifo. some bits in lsr are automatically cleared when cpu re ads the lsr register, so interrupt handling routine should be written that if once reads lsr, then keep the value th rough entire the routine because second reading lsr returns just reset value. 10.9.2.7 msr this register provides the current st ate of the control lines from the mode m (or peripheral device) to the cpu. in addition to this current-state information, four bits of the mode m status register provide change information. these bits are set to logic 1 whenever a control input from the mode m change state. they are reset to logic 0 whenever the cpu reads the modem status register. uxbase+0x18 7 6 5 4 3 2 1 0 dcd ri dsr cts ddcd teri ddsr dcts bits type function 7 this bit is the complement of the data carrier detect (nudcd) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to out2 in the mcr. 6 this bit is the complement of the ring indica tor (nuring) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to out1 in the mcr. 5 this bit is the complement of the data set ready (nudsr) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to dtr in the mcr. 4 this bit is the complement of the clear to send (nucts) input. if bit 4 (loop) of the mcr is set to a 1, this bit is equivalent to rts in the mcr. 3 this bit is the delta data carrier detect (nudcd) indicator. bit 3 indicates that the nudcd input to the chip has changed state since the last time it was read by the cpu. note: whenever bit 0, 1, 2 or 3 is set to logi c 1, a modem status interrupt is generated. 2 this bit is the trailing edge of ring indicator (teri) detector. bit 2 indicates that the nuring input to the chip has changed from a low to a high state. 1 this bit is the delta data set ready (nudsr) indicator. bit 1 indicates that the nudsr input HMS30C7202 152 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 152 - to the chip has changed state since the last time it was read by the cpu. 0 r/w this bit is the delta clear to send (nucts) indicator. bit 0 indicates that the nucts input to the chip has changed state since the last time it was read by the cpu. 10.9.2.8 scr this 8-bit read/write register does not control the uart in any way. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. uxbase+0x1c 7 6 5 4 3 2 1 0 data bits type function 7:0 r/w temporary data storage 10.9.2.9 uarten uxbase+0x30 0 sir loop back uart1 only full duplex force uart1 only siren uart1 only uarten bits type function 7:4 - reserved 3 r/w sir loop-back test ( uart1 only) 0 = sir loop-back test disable 1 = sir loop-back test enable. 2 r/w sir full-duplex force ( uart1 only) 0 = half duplex. 1 = full duplex. 1 r/w sir enable ( uart1 only) 0 = sir mode disable 1 = sir mode enable ( if you use sir function, you must set this bit with uart en bit at the same time ). 0 r/w uart enable. 0 = uart disable (power-down), uart clock stop. 1 = uart enable. 10.9.3 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr 0 = 1, ier 0 = 1) rcvr interrupts occur as follows: 1. the received data available interrupt will be i ssued to the cpu when the fifo has reached its programmed trigger level. it will be cleared as soon as the fifo drops below its programmed trigger level. 2. the iir receive data available indication also occurs when the fifo trigger le vel is reached, and like the interrupt, it is cleared when the fifo drops below the trigger level. 3. the receiver line status interrupt (iir-06), as befor e, has higher priority than the received data available (iir-04) interrupt. 4. the data ready bit (lsr 0) is set as soon as a char acter is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. 5. when rcvr fifo and receiver interrupts are enabled, rc vr fifo time-out interrupts occurs as follows: 1. a fifo time-out interrupt occurs if the following conditions exist: at least one character is in the fifo - the most recent serial character received was l onger than four continuous character times ago HMS30C7202 153 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 153 - (if two stop bits are programmed, the second one is included in this time delay) - the most recent cpu read of the fifo was lo nger than four continuous character times ago this will cause a maximum character received to interru pt issued delay of 160 ms at 300 baud with a 12-bit character. 2. character times are calculated by using the rclk input, which is the internal signal of uart for a clock signal (this makes the delay proportional to the baud rate). 3. when a time-out interrupt has o ccurred, it is cleared and the time r is reset when the cpu reads one character from the rcvr fifo. 4. when a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr 0 = 1, ier 1 = 1), xmit interrupts occurs as follows: 1. 1 the transmitter holding register interrupt (02) o ccurs when the xmit fifo is empty. it is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. 2. 2 the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre = 1 and there has not been at least two bytes at the same time in the transmit fifo since the last thre = 1. the fi rst transmitter interrupt affect changing fcr0 will be immediate if it is enabled. character time-out and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same prio rity as the current transmitter holding register empty interrupt. HMS30C7202 154 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 154 - 10.10 watchdog timer the watchdog timer (wdt) has a one-channel for moni toring system operations. if a system becomes uncontrolled and the timer counter overflows without bei ng rewritten correctly by the cpu, a reset signal is output to pmu when this watchdog function is not needed, the wdt can be used as an interval timer. in the interval timer operation, an interval timer interrupt is generated at each counter overflow. features z watchdog timer mode and interval timer mode z interrupt signal int_wdt to interrupt controller in the watchdog timer mode & interval timer mode z output signal mnreset to pmu (power management unit) z eight counter clock sources z selection whether to reset the chip internally or not z reset signal type: manual reset 10.10.1 watchdog timer operation 10.10.1.1 the watchdog timer mode to use the wdt as a watchdog timer, set the modesel and tmen bits of the wdtctrl to 1. software must prevent wdtcnt overflow by rewriting the wdtcnt value (normally by writing 0x00) before overflow occurs. if the wdtcnt fails to be rewritten and overflow due to a system crash or the like, int_wdt signal and poreset/mnreset signal are output. the int_wdt signal is not output if intren is disabled (intren = 0). wdtcnt time ox00 oxff 0x00 written in wdtcnt wtovf = 1 fault and internal reset tmen = 1 modesel = 1 figure 10-9 wdt operation in the watchdog timer mode if the rsten bit in the wdtctrl is set to 1, a signa l to reset the chip will be generated internally when wdtcnt overflows. 10.10.1.2 the interval timer mode to use the wdt as an interval timer, clear modesel in wdtctrl to 0 and set tmen to 1. a watchdog timer interrupt (int_wdt) is generated each time the time r counter overflows. this function can be used to generate interval timer interrupts at regular intervals. HMS30C7202 155 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 155 - wdtcnt time ox00 oxff itovf = 1 wdtint tmen = 1 modesel = 0 figure 10-10 wdt operation in the interval timer mode 10.10.1.3 timing of setting the overflow flag in the interval timer mode when the wdtcnt overflow s, the itovf flag is set to 1 and an watchdog timer interrupt (int_wdt) is requested. in the watchdog timer mode when the wdtcnt overflows, the wtovf bit of the wdtstat is set to 1 and a wdtout signal is output. when rsten bit is set to 1, wdtcnt overflow enables an internal reset signal to be generated for the entire chip. 10.10.1.4 timing of clearing the overflow flag when the wdt status register (wdtstat) is read, the overflow flag is cleared. 10.10.2 registers address name width default description 0x8002.b000 wdtctrl 8 0x0 timer/reset control 0x8002.b004 wdtstat 2 0x0 reset status 0x8002.b008 wdtcnt 8 timer counter table 10-11 watchdog timer register summary 10.10.2.1 wdt control register (wdtctrl) 0x8002.b000 7 6 5 4 3 2 1 0 intren modesel tmen rsten rstsel clk source sel bits type function 7 r/w enable or disable the interrupt request. 0 = disable 1 = enable 6 r/w select whether to use the wdt as a watchdog timer or interval timer. 0 = interval timer mode 1 = watchdog timer mode 5 r/w enable or disable the timer. 0 = disable 1 = enable 4 r/w select whether to reset the chip internally or not if the tcnt overflows in the watchdog timer mode. 0 = disable HMS30C7202 156 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 156 - 1 = enable 3 r/w select the type of generated internal reset if the tcnt overflows in the watchdog timer mode. 1 = manual reset enable 2:0 r/w the wdt has a clock generator which produc ts eight counter clock sources. the clock signals are obtained by dividing the fr equency of the system clock (b_clk). value clock source (system clock = 40 mhz) overflow interval 000 the system clock is divided by 2 12.8 us 001 the system clock is divided by 8 51.2 us 010 the system clock is divided by 32 204.8 us 011 the system clock is divided by 64 409.6 us 100 the system clock is divided by 256 1.64 ms 101 the system clock is divided by 512 3.28 ms 110 the system clock is divided by 2048 13.11 ms 111 the system clock is divided by 8192 52.43 ms 10.10.2.2 wdt status register (wdtstat) 0x8002.b004 1 0 itovf wtovf bits type function 7:2 - reserved 1 r set when wdtcnt has overflowed in the interval timer mode. 0 r set when wdtcnt has overflowed in the watchdog timer mode. 10.10.2.3 wdt counter (wdtcnt) 0x8002.b008 7 6 5 4 3 2 1 0 wdtcnt bits type function HMS30C7202 157 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 157 - 7:0 r 8-bit up counter. when the timer is enabled, the timer counter starts counting pulse of the selected clock source. when the value of the wdtcnt changes from 0xff-0x00(overflows), a watchdog timer overflow signal is generated in the both timer modes. the wdtcnt is initialized to 0x00 by a power-reset. 10.10.3 examples of register setting 10.10.3.1 interval timer mode tcnt = 0x00 trcr = 0xa0 b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d tcsr tcnt rstcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 b8 10 12 13 14 00111000 10111000 00111000 00 11 figure 10-11 interrupt clear in the interval timer mode 10.10.3.2 watchdog timer mode with internal reset disable tcnt = 0x00 (normally) trcr = 0xe0 HMS30C7202 158 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 158 - b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d rstcsr tcnt tcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 78 10 12 13 14 00011111 10011111 00011111 00 11 01111000 01111000 figure 10-12 interrupt clear in the watchdog timer mode with reset disable 10.10.3.3 watchdog timer mode with manual reset tcnt = 0x00 trcr = 0xf8 b_clk main_clock p_sel p_write p_stb b_res[0] b_res[1] p_a p_d rstcsr tcnt tcsr wdtint fault poreset mnreset overflow fd fe ff 00 01 10 12 13 14 01111111 11111111 01111111 11 01111000 01111000 figure 10-13 interrupt clear in the watchdog timer mode with manual reset HMS30C7202 159 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 159 - 11 debug and test interface 11.1 overview the HMS30C7202 has built-in features that enable debug and test in a number of different contexts. firstly, there are circuit structures to help with software de velopment. secondly, the device contains boundary scan cells for circuit board test. finally, the device contains some special test modes that enable the generation production patterns for the device itself. 11.2 software development debug and test interface the arm720t and piccolo processors incorporated in side HMS30C7202 contain hardware extensions for advanced debugging features. these are intended to ea se user development and de bugging of application software, operating systems, and the hardware itself. full details of the debug interfaces and their programming can be found in arm720t data sheet (arm ddi- 0087) and piccolo data sheet (arm ddi-0128). the multiice pro duct enables the arm720t and piccolo macrocells to be debugged in one environment. refer to guide to multiice (arm dui-0048). 11.3 test access port and boundary-scan HMS30C7202 contains full boundary scan on its inputs and outputs to help with circuit board test. this supports both intest and extest, allowing patterns to be applied serially to the HMS30C7202 when fixed in a board and for full circuit board connection respectively. the boundary-scan interface conforms to the ieee std. 1149.1- 1990, stan dard test access port and boundary-scan architecture. (please refer to this standard for an explanation of the terms used in this section and for a description of the ta p controller states.) the boundary-scan interface provides a means of testing the co re of the device when it is fitted to a circuit board, and a means of driving and sampling all the external pins of the device irrespective of the core state. this latter function permits testing of both the device's el ectrical connections to the circuit board, and (in conjunction with other devices on the circuit board having a similar interface) testing the integrity of the circuit board connections between devices. the interface intercep ts all external connections within the device, and each such ?cell? is then connected together to form a serial register (the boundar y scan register). the whole interface is controlled via 5 dedicated pins: tdi , tms , tck , ntrst and tdo . figure 11-1: test access port (tap) controller state transitions shows the state transitions that occur in the tap controller. HMS30C7202 160 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 160 - figure 11-1: test access port (tap) controller state transitions 11.3.1 reset the boundary-scan interface includes a state -machine controller (the tap controller). a pulldown resistor is included in the ntrst pad which holds the tap controller state machine in a safe state after power up. in order to use the boundary scan interface, ntrst should be driven high to take the tap state machine out of reset. the action of reset (either a pulse or a dc level) is as follows: ? system mode is selected (i.e. the boundary scan chai n does not intercept any of the signals passing between the pads and the core). ? idcode mode is selected. if tck is pulsed, the contents of the id register will be clocked out of tdo . note the tap controller inside HMS30C7202 contains a sc an chip register which is reset to the value b0011 thus selecting the boundary scan chain. if this register is programmed to any val ue other than b0011, then it must be reprogrammed with b0011 or a reset appl ied before boundary scan operation can be attempted. 11.3.2 pull up resistors the ieee 1149.1 standard requires pullup re sistors in the input pins. however, to ensure safe operation an internal pulldown is present in the ntrst pin and therefore will have to be driven high when using this interface. HMS30C7202 161 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 161 - pin name internal resistor tclk pullup ntrst pulldown tms pullup tdi pullup 11.3.3 instruction register the instruction register is 4 bits in length. there is no parity bit. the fixed value loaded into th e instruction register durin g the capture-ir controller state is: 0001. 11.3.4 public instructions the following public instructions are supported: instruction binary code extest 0000 sample/preload 0011 clamp 0101 highz 0111 clampz 1001 intest 1100 idcode 1110 bypass 1111 in the descriptions that follow, tdi and tms are sampled on the rising edge of tck and all output transitions on tdo occur as a result of the falling edge of tc k. extest (0000) the bs (boundary-scan) register is placed in test mode by the extest instruction.the extest instruction connects the bs register between tdi and tdo .when the instruction register is loaded with the extest instruction, all the boundary-scan cells ar e placed in their test mode of operation. in the capture-dr state, inputs from the system pins and outputs from the boundary-scan output cells to the system pins are captured by t he boundary-scan cells. in the shift-dr st ate, the previously captured test data is shifted out of the bs register via the tdo pin, whilst new test data is shifted in via the tdi pin to the bs register parallel input latch. in t he update-dr state, the ne w test data is transferred into the bs register parallel output latch. note that this data is applied imme diately to the system logic and system pins. the first extest vector should be clocked into the boundary- scan register, using the sam ple/preload instruction, prior to selecting extest to ensure that known data is applied to the system logic. sample/preload (0011) the bs (boundary-scan) register is placed in normal (system) mode by the sample/preload instruction. the sample/preload instruction connects the bs register between tdi and tdo . when the instruction register is l oaded with the sample/preload instru ction, all the boundary-scan cells are placed in their normal sy stem mode of operation. in the capture-dr state, a snapshot of the signals at the boundary-scan cells is taken on the rising edge of tck . normal system operation is unaffected. in the shift- dr state, the sampled test data is shifted out of the bs register via the tdo pin, whilst new data is shifted in via the tdi pin to preload the bs register parallel input latch. in the update-dr stat e, the preloaded data is transferred into the bs register parallel output latch. note that this data is not applied to the system logic or system pins while the sample/preload HMS30C7202 162 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 162 - instruction is active. this instruction should be used to preload the boundary-scan register with known data prior to selecting the intest or extest instructions. clamp (0101) the clamp instructi on connects a 1 bit shift regist er (the bypass register) between tdi and tdo . when the clamp instruction is loaded into the in struction register, the st ate of all output signals is defined by the values previously loaded into the boundary-scan register. a guar ding pattern should be pre-loaded into the boundary- scan register using the sample/preload instruction pr ior to selecting the clamp instruction. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that t he first bit shifted out will be a zero. the bypass register is not affected in t he update-dr state. highz (0111) the highz instruction connects a 1 bit sh ift register (the bypass register) between tdi and tdo . when the highz instruction is loaded into the in struction register, all outputs are placed in an inactive drive state. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that t he first bit shifted out will be a zero. the bypass register is not affected in t he update-dr state. clampz (1001) the clampz instruction connects a 1 bit shift register (the bypass register) between tdi and tdo . when the clampz instruction is loaded into the instruction register, all outputs are placed in an inactive drive state, but the data supplied to the disabled output drivers is derived from the boundary-scan cells. the purpose of this instruction is to ensure, during production testing, that each output driver can be disabled when its data input is either a 0 or a 1. a guarding pattern (specified for this device at the end of this section) should be pre- loaded into the boundary-scan register using the sam ple/preload instruction prior to selecting the clampz instruction. in the capture- dr state, a logic 0 is c aptured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that the first bit shifted out will be a zero. the by pass register is not affect ed in the update-dr state. intest (1100) the bs (boundary-scan) register is pl aced in test mode by the intest in struction. the intest instruction connects the bs register between tdi and td o. when the instruction register is loaded with the intest instruction, all the boundary-scan cells are placed in their test mode of operation. in the capture-dr state, the complement of the data supplied to the core logic from input boundar y-scan cells is captured, while the true value of the data that is output from the core logic to output bo undary- scan cells is captured. note that capture-dr captures the complemented value of the input cells for test ability reasons. in the shift-dr state, the previously captured test data is shifted out of the bs register via the tdo pin, whilst new test data is shifted in via the tdi pin to the bs register parallel input latch. in the update-dr state, the new test data is transferred into the bs register parallel output latch. no te that this data is applied immediately to the system logic and system pins. the first intest vector should be clocked into the boundary-scan register, using the sample/preload instruction, prior to selecting intest to ensure that known data is applied to the system logic. single-step operation is possi ble using the intest instruction. idcode (1110) the idcode instruction connects the device identification regist er (or id register) between tdi and td o. the id register is a 32-bit register that allows the ma nufacturer, part number and version of a component to be determined through the tap. the idcode returned will be that for the arm720t core. when the instruction register is loaded with the idcode in struction, all the boundary-scan cells are placed in their normal (system) mode of operation. in the capture-dr state, the device identification c ode (specified at the end of this section) is captured by the id register. in the shift-dr state, the pr eviously captured device identification code is shifted out of the id register via the tdo pin, whilst data is shifted in via the tdi pin into the id register. in the update-dr state, the id register is unaffected. bypass (1111) the bypass instruction connects a 1 bit sh ift register (the bypass register) between tdi and td o. when the bypass instruction is loaded into th e instruction register, all the boundary-scan cells are placed in their normal (system) mode of operation. th is instruction has no effect on t he system pins. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr stat e, test data is shifted into the bypass HMS30C7202 163 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 163 - register via tdi and out via tdo after a delay of one tck cycle. note that the first bit shifted out will be a zero. the bypass register is not affe cted in the update-dr state. 11.3.5 test data registers figure 11-2: boundary scan block diagram bypass register purpose: this is a single bit register which can be selected as the path between tdi and tdo to allow the device to be bypassed during boundary-scan testing. length: 1 bit operating mode: when the bypass in struction is the current in struction in the instruct ion register, serial data is transferred from tdi to tdo in the shift-dr state with a delay of one tck cycle. there is no parallel output from the bypass register. a logic 0 is loaded from the parallel input of the bypass register in the capture-dr state. boundary scan (bs) register purpose: the bs register consists of a serially connected set of cells around the periphery of the device, at the interface between the core logic and the system inpu t/output pads. this register can be used to isolate the HMS30C7202 core logic HMS30C7202 164 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 164 - core logic from the pins and then apply tests to the core logic, or conversely to isol ate the pins from the core logic and then drive or monitor the sy stem pins. operating modes: the bs r egister is selected as the register to be connected between tdi and tdo only during the sample/preload, extest and intest instructions. values in the bs register are used, but are not changed, during the clamp and clampz instructions. in the normal (system) mode of operation, straight-through connections between the core logic and pins are maintained and normal system operation is unaffected. in test mode (i.e. when either extest or intest is the currently selected instruction), val ues can be applied to the core logic or output pins independently of the actual values on the input pins and core logic outputs respectively. on the HMS30C7202 all of the boundary scan cells include an update register and thus all of t he pins can be controlled in the above manner. additional boundary-scan cells are interposed in the scan c hain in order to control t he enabling of tristateable buses. the values stored in the bs register after power-u p are not defined. similarly, the values previously clocked into the bs register are not guaranteed to be maintained across a boundary scan reset (from forcing ntrst low or entering the te st logic reset state). single-step operation HMS30C7202 is a static design and t here is no minimum clock speed. it c an therefore be single-stepped while the intest instruction is sele cted and the plls are bypassed. this can be achieved by serializing a parallel stimulus and clocking the resulting serial vectors into the boundary-scan register. when the boundar y-scan register is updated, new test stimuli are applied to the core logic inputs; the effect of these stim uli can then be observed on the core logic outputs by capturing them in the boundary-scan register. 11.3.6 boundary scan interface signals figure 11-3: boundary scan general timing HMS30C7202 165 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 165 - figure 11-4: boundary scan tristate timing figure 11-5: boundary scan reset timing symbol parameter min max tbscl tck low period 50 - tbsch tck high period 50 - tbsis tms, tdi setup to tckr 0 - tbsih tms, tdi hold from tckr 2 - tbsoh tdo output hold from tckf 3 - tbsod tdo output delay from tckf - 20 tbsss test mode data in setup to tckr 2 - tbssh test mode data in hold from tckf 5 - tbsdh test mode data out hold from tckf 3 - tbsdd test mode data out delay from tckf - 20 tbsoe tdo output enable delay from tckf 2 15 tbsoz test mode data enable delay from tckf 2 15 tbsde tdo output disable delay from tckf 2 15 tbsdz test mode data disable delay from tckf 2 15 tbsr ntrst minimun pulse width 25 - tbsrs tms setup to ntrstr 20 - tbsrh tms hold from ntrstr 20 - the ac parameters are based on simulation re sults using 0.0pf circuit signal loads. delays should be calculated using manufacturers output derating values for the actual circuit capacitance loading. the correspondence between boundary-scan cells and syst em pins, system direction controls and system output enables is shown below. the cells are listed in the order in which they are connected in the boundary- scan register, starting with the cell closest to tdi. all outputs are three-state outputs. all boundary-scan register cells at input pins can apply tests to the on-chip system logic. extest/clamp guard values specified in the table below should be clocked into the boundary-scan register (using the sample/preload instructi on) before the extest, clamp or cl ampz instructions are selected to ensure that known data is applied to the system logic during the test. the intest guard values shown in the table below should be clocked into the boundary-sc an register (using the sample/preload instruction) before the intest instruction is selected to ensure t hat all outputs are disabled. an asterisk in the guard HMS30C7202 166 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 166 - value column indicates that any value can be submitt ed (as test requires), but ones and zeros should always be placed as shown. num pad cell name pin type output enable bs cell guard value 1 uld4 ld[4] out - 0 * 2 uld3 ld[3] in - * * 3 uld3 ld[3] out - * * 4 uld3 - outen ldpadouten[3] 1 * 5 uld2 ld[2] in - * * 6 uld2 ld[2] out - * * 7 uld2 - outen ldpadouten[2] 1 * 8 uld1 ld[1] in - * * 9 uld1 ld[1] out - * * 10 uld1 - outen ldpadouten[1] 1 * 11 uld0 ld[0] in - * * 12 uld0 ld[0] out - * * 13 uld0 - outen ldpadouten[0] 1 * 14 ukscano0 kscano[0] in - * * 15 ukscano0 kscano[0] out - * * 16 ukscano0 - outen muxportaouten[0] 1 * 17 ukscano1 kscano[1] in - * * 18 ukscano1 kscano[1] out - * * 19 ukscano1 - outen muxportaouten[1] 1 * 20 ukscano2 kscano[2] in - * * 21 ukscano2 kscano[2] out - * * 22 ukscano2 - outen muxportaouten[2] 1 * 23 ukscano3 kscano[3] in - * * 24 ukscano3 kscano[3] out - * * 25 ukscano3 - outen muxportaouten[3] 1 * 26 ukscano4 kscano[4] in - * * 27 ukscano4 kscano[4] out - * * 28 ukscano4 - outen muxportaouten[4] 1 * 29 ukscano5 kscano[5] in - * * 30 ukscano5 kscano[5] out - * * 31 ukscano5 - outen muxportaouten[5] 1 * 32 ukscano6 kscano[6] in - * * 33 ukscano6 kscano[6] out - * * 34 ukscano6 - outen muxportaouten[6] 1 * 35 ukscano7 kscano[7] in - * * 36 ukscano7 kscano[7] out - * * 37 ukscano7 - outen muxportaouten[7] 1 * 38 ukscani0 kscani[0] in - * * 39 ukscani0 kscani[0] out - * * 40 ukscani0 - outen muxportaouten[8] 1 * 41 ukscani1 kscani[1] in - * * 42 ukscani1 kscani[1] out - * * 43 ukscani1 - outen muxportaouten[9] 1 * 44 ukscani2 kscani[2] in - * * 45 ukscani2 kscani[2] out - * * 46 ukscani2 - outen muxportaouten[10] 1 * 47 ukscani3 kscani[3] in - * * 48 ukscani3 kscani[3] out - * * 49 ukscani3 - outen muxportaouten[11] 1 * 50 ukscani4 kscani[4] in - * * 51 ukscani4 kscani[4] out - * * 52 ukscani4 - outen muxportaouten[12] 1 * 53 ukscani5 kscani[5] in - * * 54 ukscani5 kscani[5] out - * * HMS30C7202 167 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 167 - 55 ukscani5 - outen muxportaouten[13] 1 * 56 ukscani6 kscani[6] in - * * 57 ukscani6 kscani[6] out - * * 58 ukscani6 - outen muxportaouten[14] 1 * 59 ukscani7 kscani[7] in - * * 60 ukscani7 kscani[7] out - * * 61 ukscani7 - outen muxportaouten[15] 1 * 62 uatsxp atsxp in - * * 63 uatsxp atsxp out - * * 64 uatsxp - outen atsxpen 1 * 65 uatsxn atsxn out - 0 * 66 uatsxn - outen atsxnen 1 * 67 uatsyp atsyp in - * * 68 uatsyp atsyp out - * * 69 uatsyp - outen atsypen 1 * 70 uatsyn atsyn in - * * 71 uatsyn atsyn out - * * 72 uatsyn - outen atsynen 1 * 73 unpmwakeup npmwakeup in - * 0 74 unpor npor in - * 0 75 unreset nreset in - * * 76 unreset nreset out - * * 77 unreset - outen nreseten 1 * 78 upmadapok pmadapok in - * 0 79 upmbatok pmbatok in - * 0 80 unpllenable npllenable in - * 0 81 unuring nuring in * * 82 unuring nuring out * * 83 unuring - outen muxnportbouten[0] 1 * 84 unudtr nudtr in - * * 85 unudtr nudtr out - * * 86 unudtr - outen muxnportbouten[1] 1 * 87 unucts nucts in - * * 88 unucts nucts out - * * 89 unucts - outen muxnportbouten[2] 1 * 90 unurts nurts in - * * 91 unurts nurts out - * * 92 unurts - outen muxnportbouten[3] 1 * 93 unudsr nudsr in - * * 94 unudsr nudsr out - * * 95 unudsr - outen muxnportbouten[4] 1 * 96 unudcd nudcd in - * * 97 unudcd nudcd out - * * 98 unudcd - outen muxnportbouten[5] 1 * 99 uusin0 usin0 in - * 0 100 uusout0 usout0 out - 0 * 101 uusin1 usin1 in - * 0 102 uusout1 usout1 out - 0 * 103 ucantx0 cantx[0] in - * * 104 ucantx0 cantx[0] out - * * 105 ucantx0 - outen muxnportcouten[1] 1 * 106 ucanrx0 canrx[0] in - * * 107 ucanrx0 canrx[0] out - * * 108 ucanrx0 - outen muxnportcouten[2] 1 * 109 uportb6 portb[6] in - * * 110 uportb6 portb[6] out - * * 111 uportb6 - outen muxnportbouten[6] 1 * 112 uportb7 portb[7] in - * * 113 uportb7 portb[7] out - * * HMS30C7202 168 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 168 - 114 uportb7 - outen muxnportbouten[7] 1 * 115 uportb8 portb[8] in - * * 116 uportb8 portb[8] out - * * 117 uportb8 - outen muxnportbouten[8] 1 * 118 uportb9 portb[9] in - * * 119 uportb9 portb[9] out - * * 120 uportb9 - outen muxnportbouten[9] 1 * 121 uportb10 portb[10] in - * * 122 uportb10 portb[10] out - * * 123 uportb10 - outen muxnportbouten[10] 1 * 124 uportb11 portb[11] in - * * 125 uportb11 portb[11] out - * * 126 uportb11 - outen muxnportbouten[11] 1 * 127 utimerout timerout in - * * 128 utimerout timerout out - * * 129 utimerout - outen muxnportccuten[0] 1 * 130 upsdat psdat in - * * 131 upsdat psdat out - * * 132 upsdat - outen muxnportccuten[3] 1 * 133 upsclk psclk in - * * 134 upsclk psclk out - * * 135 upsclk - outen muxnportccuten[4] 1 * 136 upwm0 pwm[0] in - * * 137 upwm0 pwm[0] out - * * 138 upwm0 - outen muxnportccuten[5] 1 * 139 upwm1 pwm[1] in - * * 140 upwm1 pwm[1] out - * * 141 pwm1 - outen muxnportccuten[6] 1 * 142 ucantx1 cantx[1] in - * * 143 ucantx1 cantx[1] out - * * 144 ucantx1 - outen - 1 * 145 ucanrx1 canrx[1] in muxnportecuten[23] * * 146 ucanrx1 canrx[1] out - * * 147 ucanrx1 - outen muxnportecuten[22] 1 * 148 ummccmd mmccmd in - * * 149 ummccmd mmccmd out - * * 150 ummccmd - outen muxnportecuten[18] 1 * 151 ummcdat mmcdat in - * * 152 ummcdat mmcdat out - * * 153 ummcdat - outen muxnportecuten[19] 1 * 154 unmmccd nmmccd in - * * 155 unmmccd nmmccd out - * * 156 unmmccd - outen muxnportecuten[20] 1 * 157 ummcclk mmcclk in - * * 158 ummcclk mmcclk out - * * 159 ummcclk - outen muxnportecuten[21] 1 * 160 undmareq ndmareq in - * * 161 undmareq ndmareq out - * * 162 undmareq - outen muxnportcouten[7] 1 * 163 undmaack ndmaack in - * * 164 undmaack ndmaack out - * * 165 undmaack - outen muxnportcouten[8] 1 * 166 unrcs3 nrcs[3] in - * * 167 unrcs3 nrcs[3] out - * * 168 unrcs3 - outen muxnportcouten[10] 1 * 169 unrcs2 nrcs[2] in - * * 170 unrcs2 nrcs[2] out - * * 171 unrcs2 - outen muxnportcouten[9] 1 * 172 unrcs1 nrcs[1] out - 0 * HMS30C7202 169 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 169 - 173 unrcs0 nrcs[0] out - 0 * 174 ubootbit1 bootbit[1] in - * 0 175 ubootbit0 bootbit[0] in - * 0 176 unroe nroe out 0 * 177 uexprdy exprdy in - * 0 178 unrwe3 nrwe[3] in - * * 179 unrwe3 nrwe[3] out - * * 180 unrwe3 - outen muxnporteouten[17] 1 * 181 unrwe2 nrwe[2] in - * * 182 unrwe2 nrwe[2] out - * * 183 unrwe2 - outen muxnporteouten[16] 1 * 184 unrwe1 nrwe[1] out - 0 * 185 unrwe0 nrwe[0] out - 0 * 186 urd31 rd[31] in - * * 187 urd31 rd[31] out - * * 188 urd31 - outen muxnporteouten[15] 1 * 189 urd30 rd[30] in - * * 190 urd30 rd[30] out - * * 191 urd30 - outen muxnporteouten[14] 1 * 192 urd29 rd[29] in - * * 193 urd29 rd[29] out - * * 194 urd29 - outen muxnporteouten[13] 1 * 195 urd28 rd[28] in - * * 196 urd28 rd[28] out - * * 197 urd28 - outen muxnporteouten[12] 1 * 198 urd27 rd[27] in - * * 199 urd27 rd[27] out - * * 200 urd27 - outen muxnporteouten[11] 1 * 201 urd26 rd[26] in - * * 202 urd26 rd[26] out - * * 203 urd26 - outen muxnporteouten[10] 1 * 204 urd25 rd[25] in - * * 205 urd25 rd[25] out - * * 206 urd25 - outen muxnporteouten[9] 1 * 207 urd24 rd[24] in - * * 208 urd24 rd[24] out - * * 209 urd24 - outen muxnporteouten[8] 1 * 210 urd23 rd[23] in - * * 211 urd23 rd[23] out - * * 212 urd23 - outen muxnporteouten[7] 1 * 213 urd22 rd[22] in - * * 214 urd22 rd[22] out - * * 215 urd22 - outen muxnporteouten[6] 1 * 216 urd21 rd[21] in - * * 217 urd21 rd[21] out - * * 218 urd21 - outen muxnporteouten[5] 1 * 219 urd20 rd[20] in - * * 220 urd20 rd[20] out - * * 221 urd20 - outen muxnporteouten[4] 1 * 222 urd19 rd[19] in - * * 223 urd19 rd[19] out - * * 224 urd19 - outen muxnporteouten[3] 1 * 225 urd18 rd[18] in - * * 226 urd18 rd[18] out - * * 227 urd18 - outen muxnporteouten[2] 1 * 228 urd17 rd[17] in - * * 239 urd17 rd[17] out - * * 230 urd17 - outen muxnporteouten[1] 1 * 231 urd16 rd[16] in - * * HMS30C7202 170 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 170 - 232 urd16 rd[16] out - * * 233 urd16 - outen muxnporteouten[0] 1 * 234 urd15 rd[15] in - * * 235 urd15 rd[15] out - * * 236 urd15 - outen nrden[1] 1 * 237 urd14 rd[14] in - * * 238 urd14 rd[14] out jnrden[1] * * 239 urd13 rd[13] in - * * 240 urd13 rd[13] out jnrden[1] * * 241 urd12 rd[12] in - * * 242 urd12 rd[12] out jnrden[1] * * 243 urd11 rd[11] in - * * 244 urd11 rd[11] out jnrden[1] * * 245 urd10 rd[10] in - * * 246 urd10 rd[10] out jnrden[1] * * 247 urd9 rd[9] in - * * 248 urd9 rd[9] out jnrden[1] * * 249 urd8 rd[8] in - * * 250 urd8 rd[8] out jnrden[1] * * 251 urd7 rd[7] in - * * 252 urd7 rd[7] out - * * 253 urd7 - outen nrden[0] 1 * 254 urd6 rd[6] in - * * 255 urd6 rd[6] out jnrden[0] * * 256 urd5 rd[5] in - * * 257 urd5 rd[5] out jnrden[0] * * 258 urd4 rd[4] in - * * 259 urd4 rd[4] out jnrden[0] * * 260 urd3 rd[3] in - * * 261 urd3 rd[3] out jnrden[0] * * 262 urd2 rd[2] in - * * 263 urd2 rd[2] out jnrden[0] * * 264 urd1 rd[1] in - * * 265 urd1 rd[1] out jnrden[0] * * 266 urd0 rd[0] in - * * 267 urd0 rd[0] out jnrden[0] * * 268 ura0 ra[0] out - 0 * 269 ura1 ra[1] out - 0 * 270 ura2 ra[2] out - 0 * 271 ura3 ra[3] out - 0 * 272 ura4 ra[4] out - 0 * 273 ura5 ra[5] out - 0 * 274 ura6 ra[6] out - 0 * 275 ura7 ra[7] out - 0 * 276 ura8 ra[8] out - 0 * 277 ura9 ra[9] out - 0 * 278 ura10 ra[10] out - 0 * 279 ura11 ra[11] out - 0 * 280 ura12 ra[12] out - 0 * 281 ura13 ra[13] out - 0 * 282 ura14 ra[14] out - 0 * 283 ura15 ra[15] out - 0 * 284 ura16 ra[16] out - 0 * 285 ura17 ra[17] out - 0 * 286 ura18 ra[18] out - 0 * 287 ura19 ra[19] out - 0 * 288 ura20 ra[20] out - 0 * 289 ura21 ra[21] out - 0 * 290 ura22 ra[22] out - 0 * HMS30C7202 171 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 171 - 291 ura23 ra[23] out - 0 * 292 ura24 ra[24] in - * * 293 ura24 ra[24] out - * * 294 ura24 - outen muxnporteouten[24] 1 * 295 usa3 sa[3] out - 0 * 296 usa4 sa[4] out - 0 * 297 usa2 sa[2] out - 0 * 298 usa5 sa[5] out - 0 * 299 usa1 sa[1] out - 0 * 300 usa6 sa[6] out - 0 * 301 usa0 sa[0] out - 0 * 302 usa7 sa[7] out - 0 * 303 usa8 sa[8] out - 0 * 304 usa9 sa[9] out - 0 * 305 usa10 sa[10] out - 0 * 306 usa11 sa[11] out - 0 * 307 usa12 sa[12] out - 0 * 308 usa13 sa[13] out - 0 * 309 usa14 sa[14] out - 0 * 310 unscs1 nscs[1] out - 0 * 311 unscs0 nscs[0] out - 0 * 312 unsras nsras out - 0 * 313 unrcas nscas out - 0 * 314 unswe nswe out - 0 * 315 uscke1 scke[1] out - 0 * 316 uscke0 scke[0] out - 0 * 317 usclk sclk in - * * 318 usclk sclk out - * * 319 usclk - outen 1?b0 1 * 320 usdqmu sdqmu out - 0 * 321 usdqml sdqml out - 0 * 322 usd8 sd[8] in - * * 323 usd8 sd[8] out jnsden * * 324 usd7 sd[7] in - * * 325 usd7 sd[7] out jnsden * * 326 usd9 sd[9] in - * * 327 usd9 sd[9] out jnsden * * 328 usd6 sd[6] in - * * 329 usd6 sd[6] out jnsden * * 330 usd10 sd[10] in - * * 331 usd10 sd[10] out jnsden * * 332 usd5 sd[5] in - * * 333 usd5 sd[5] out jnsden * * 334 usd11 sd[11] in - * * 335 usd11 sd[11] out jnsden * * 336 usd4 sd[4] in - * * 337 usd4 sd[4] out jnsden * * 338 usd12 sd[12] in - * * 339 usd12 sd[12] out jnsden * * 340 usd3 sd[3] in - * * 341 usd3 sd[3] out jnsden * * 342 usd13 sd[13] in - * * 343 usd13 sd[13] out jnsden * * 344 usd2 sd[2] in - * * 345 usd2 sd[2] out jnsden * * 346 usd14 sd[14] in - * * 347 usd14 sd[14] out jnsden * * 348 usd1 sd[1] in - * * 349 usd1 sd[1] out jnsden * * HMS30C7202 172 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 172 - 350 usd15 sd[15] in - * * 351 usd15 sd[15] out - * * 352 usd15 - outen nsden 1 * 353 usd0 sd[0] in - * * 354 usd0 sd[0] out jnsden * * 355 ullp llp out - 0 * 356 ulac lac out - 0 * 367 ulblen lblen in - * * 358 ulblen lblen out - * * 359 ulblen - outen muxnportdouten[8] 1 * 360 ulcp lcp out - 0 * 361 ulfp lfp out - 0 * 362 ulcden lcden out - 0 * 363 uld15 ld[15] in - * * 364 uld15 ld[15] out - * * 365 uld15 - outen muxnportdouten[7] 1 * 366 uld14 ld[14] in - * * 367 uld14 ld[14] out - * * 368 uld14 - outen muxnportdouten[6] 1 * 369 uld13 ld[13] in - * * 370 uld13 ld[13] out - * * 371 uld13 - outen muxnportdouten[5] 1 * 372 uld12 ld[12] in - * * 373 uld12 ld[12] out - * * 374 uld12 - outen muxnportdouten[4] 1 * 375 uld11 ld[11] in - * * 376 uld11 ld[11] out - * * 377 uld11 - outen muxnportdouten[3] 1 * 378 uld10 ld[10] in - * * 379 uld10 ld[10] out - * * 380 uld10 - outen muxnportdouten[2] 1 * 381 uld9 ld[9] in - * * 382 uld9 ld[9] out - * * 383 uld9 - outen muxnportdouten[1] 1 * 384 uld8 ld[8] in - * * 385 uld8 ld[8] out - * * 386 uld8 - outen muxnportdouten[0] 1 * 387 uld7 ld[7] out - 0 * 388 uld6 ld[6] out - 0 * 389 uld5 ld[5] out - 0 * 11.4 production test features in order to generate test vectors su itable for use on a production tester by the chip manufacturer, some special test modes have been introduced. these modes come into operation whenever the pin ntest is forced low. full details of these modes are available from arm in a special test document on request. HMS30C7202 173 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 173 - 12 electrical characteristics 12.1 absolute maximum ratings symbol parameter min max units v dd v in i in t stg power supply voltage dc input voltage dc input current storage temperature -0.5 -0.3 -50 -65 4.6 6 50 150 v v ma c note : permanent damage can be occur if maximum ratings are exceeded. device modules may not operate normally while being exposed to electrical extremes. although sections of the device contain circuitry to protect against damages from high static voltages or electrical fi elds, take normal pre-cautions to avoid exposure to voltages higher than maximum rated voltages. recommended operating range symbol parameter min max units vdd (3.3v) vdd (2.5v) t opr dc power supply voltage (3.3v) ? use for i/o dc power supply voltage (2.5v) ? use for a core operating temperature (industrial temperature) 3.0 2.3 -40 3.6 2.7 85 v v c HMS30C7202 174 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 174 - 12.2 dc characteristics all characteristics are specified at v dd = 3.0 to 3.6v and v ss = 0v over the junction temperature range of 0 to 100 c. power dissipation symbol parameter min max units p d p dwn [run mode] with lcd @70.04mhz without lcd @70.04mhz [deep sleep mode] rtc enable rtc disable 120 30 190 140 160 70 mw mw uw uw cmos/ttl compatible pin symbol parameter min max conditions v il low-level input voltage 0.3xv dd guaranteed input low voltage v ih high-level input voltage 0.7xv dd guaranteed input high voltage v ol low-level output voltage 0.4 v 0.4 v 0.4 v i ol = 1 ma (*group a) i ol = 2 ma (group b) i ol = 4 ma (group c) v oh high-level output voltage 2.4 v 2.4 v 2.4 v i oh = -1 ma (group a) i oh = -2 ma (group b) i oh = -4 ma (group c) i il input low current -10 ua 10 ua v in -v ss i ih input high current -10 ua 10 ua v in =v dd i oz 3-state output leakage current -10 ua 10 ua v pad = v ss or v dd * : it means the drive strength (gr oup a = 1, group b = 2, group c = 4) refer to gpio part (page 122) i/o circuit pull-up pin the following current values are used fo r i/os with internal pull-up devices. symbol parameter min(v in = v ss ) max(v in = v dd ) i pu pull-up -100 ua - 4 ua note : the following pins are used with internal pull-up devices. tdi, tck, tms, pmadaok, pmbatok, ntest, npmwakeup i/o circuit pull-down pin the following current values are used fo r i/os with internal pull-down devices. symbol parameter min(v in = v ss ) max(v in = v dd ) i pd pull-down 4 ua 100 ua note : the following pins are used with internal pull-down devices. ntrst, testscan, npllenable, scan_en HMS30C7202 175 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 175 - 12.3 a/d converter electrical characteristics symbol paramter test condition min typ max unit normal aclk=8mhz * input=av ref v fin=2khz ramp 6.0 ma i dd power down aclk=8mhz 60 ua an** analog input voltage avss+0.2 avref-0.2 v accuracy resolution 10 bits inl integral non-linearity aclk=8mhz input=0 - av ref v fin=2khz ramp 2.0 lsb dnl differential non-linearity aclk=8mhz input=0 - av ref v fin=2khz ramp 1.0 lsb snr signal-to-noise ratio f sample = 500ksps fin = 2khz 51 54 db sndr signal-to-noise distortion ratio 49 52 db aclk 2 4 8 mhz t c conversion time t c = [aclk/16] -1 2 4 8 us av ref *** analog reference voltage avdd v t cal power-up time calibration time 22 ms thd total harmonic distortion 51 54 db avdd analog power 3.0 3.3 3.6 v dvdd digital power 3.0 3.3 3.6 v fin analog input frequency 5 khz (for test, analog input freq. = 2khz, aclk=8mhz, avdd=dvdd=av ref =3.3v, temperature=25c) aclk : to determine electrical characterist ic of adc, used 8mhz clock as aclk. but for 7202 adc, used 3.6864mhz for aclk. an* : analog input is sample and hold with 500 ? resistor and 300 ff capacitor in series and connected with gate of cmos transistor. so, in normal, input resistance of an analog input pin has a co uple of mega ohms. avref** : the equivalent impedance of avref is about 5k ? of resistance to gnd. HMS30C7202 176 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 176 - 12.4 d/a converter electrical characteristics symbol paramter test condition min typ max unit normal f clk =50khz 3.6 4.1 4.6 ma i dd power down tbd ua accuracy resolution 8 bits inl integral non-linearity dc -0.6 +0.6 lsb dnl differential non-linearity dc -0.2 +0.2 lsb snr signal-to-noise ra tio 47.5 47.7 47.8 db sndr signal-to-noise distortion ratio 47.1 47.4 47.7 db thd total harmonic distortion f con =50khz temperature=25c 57.5 61.8 65.9 db f con conversion speed 50 khz tr/tf rise/fall time with 10% error 0.4 us v out (p-p) output voltage range 1.025 2.675 v t d output delay time 1.4 us the current drive capability is about 500ua on output of dac. typical load is about 10k ? of resistance and 10pf of c apacitance on output of dac. HMS30C7202 177 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 177 - 12.5 ac characteristics 12.5.1 static memory interface 12.5.1.1 read access timing (single mode) bclk nrcs nroe a ra b c trec tsu(a) tho(a) rd tsu(d) tho(d) tsu(ce0) symbol parameter min max unit tsu(a) address to nrcs falling-edge setup time 25 tho(a) nroe rising-edge to address hold time 0 tsu(ce0) nrcs falling-edge to nroe falling-edge setup time 13 tho(ce0) nroe rising-edge to nrcs rising-edge setup time -13 tho(ce1) nroe or nrwe rising-edge to nrcs falling-edge hold time 15 tsu(ce1) nrcs rising-edge to nroe or nrwe falling-edge setup time 25 trec nroe negate to start of next cycle 50 tsu(d) data setup time before latch 5 tho(d) data hold time after latch 0 ns timing values for read access in single mode data transfer memory configuration register setting = 0x060 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 0 0 0 0 HMS30C7202 178 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 178 - 12.5.1.2 read access timing (burst mode) bclk nrcs nroe n ra n+1 n+2 n+3 rd tsu(ce0) tsu(ce1) tho(a) tsu(d) tho(d) tho(ce1) tsu(a) symbol parameter min max unit tsu(a) address to nrcs falling-edge setup time 13 tho(a) nroe rising-edge to address hold time -15 tsu(ce0) nrcs falling-edge to nroe falling-edge setup time 13 tho(ce0) nroe rising-edge to nrcs rising-edge setup time -13 tho(ce1) nroe or nrwe rising-edge to nrcs falling-edge hold time 25 tsu(ce1) nroe or nrwe rising-edge to nrcs falling-edge setup time 50 tsu(d) data setup time before latch 5 tho(d) data hold time after latch 0 ns timing values for read access in burst mode data transfer memory configuration register setting = 0xe00 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 0 0 0 0 0 0 0 HMS30C7202 179 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 179 - 12.5.1.3 write access timing bclk nrcs nrwe n r a n+1 n+2 n+3 rd trec(wr) tsu(a) tsu(ce0) tho(a) tloz(d) tacc thiz(d) tho(ce0) symbol parameter min max unit tsu(a) address to nrwe falling-edge setup time 15 tho(a) nrwe rising-edge to address hold time 0 tsu(ce0) nrcs falling-edge to nrwe falling-edge setup time 15 tho(ce0) nrwe rising-edge to nrcs rising-edge setup time 27 tho(ce1) nroe or nrwe rising-edge to nrcs falling-edge hold time 39 tsu(ce1) nrcs rising-edge to nroe or nrwe falling-edge setup time 25 trec(wr) nrwe negate to start of next cycle 26 thiz(d) nrwe rising edge to d hi-z delay 25 tacc write access time 4.5 tloz(d) nrwe falling-edge to d driven 0 ns timing values for write access memory configuration register setting = 0x068 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 1 0 0 0 HMS30C7202 180 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 180 - 12.5.2 sdram interface condition : 70mhz cpu clock speed ras/cas timing /ras /cas 42ns single read operation /ras /cas dataout effective data 42~46ns 84~88ns single write operation /ras /cas /we datain effective data 14~15ns 14~15ns 14~15ns effective data burst read operation /ras /cas dataout burst write operation /ras /cas /we datain effective data effective data effective data effective data 14~15ns 14~15ns 14~15ns 14~15ns effective data effective data effective data effective data 11~12ns 3ns 42~46ns HMS30C7202 181 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 181 - 12.5.3 lcd interface lcd controller timing(stn mode) lcd controller timing(active-tft mode) symbol parameter min typ max unit t1 lcp high time 1 - 16 tclk(notes) t2 lcp low time 1 - 17 tclk t3 llp front-porch 1 - 256 tclk t4 llp pulse width 1 - 256 tclk t5 llp back-porch 1 - 256 tclk t6 failing llp to lfp(lac) toggle 1 - 256 tclk HMS30C7202 182 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 182 - t7 rising lcp to display data change tbd tbd ns t8 vsync width 1 64 thperiod(notes) t9 vsync back-porch 1 256 thperiod t10 vsync front-porch 1 256 thperiod t11 hsync width 1 256 tclk t12 hsync back-porch 1 - 256 tclk t13 hsync front-porch 1 - 256 tclk t14 dot clock period 1 - - tclk lcd interface signal timing parameters note : tclk is bclk or vclk(lcd controller internal clock source : 31.5 or 40 mhz). thperiod max = 1408 tclk stn mode signal delay symbol parameter min max tmlcdod output delay time from lcp rising - 5 tmlcdoh output hold time from lcp rising - -5 stn mode signal delay parameters timing values are derived from simulations using 0pf signal loading. actual circuit output delays should be calculated by adding manufacturers signal load de-rating delay values. tft mode signal delay symbol parameter min max ttftod output delay time from lcp rising - 3 ttftoh output hold time from lcp rising - -3 tft mode signal delay parameters timing values are derived from simulations using 0pf signal loading. actual circuit output delays should be calculated by adding manufacturers signal load de-rating delay values. HMS30C7202 183 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 183 - 12.5.4 uart(universal asynchronous receiver transmitter) serial out(txd) start data(5-8) parity stop(1-2) thr update xmit empty thr empty intr baud clock data output bit 2 bit 3 bit 1 t bit = 16 baud clock t baud t baud +5ns t bit serial in(txd) s d p st 1 0 xmt fifo data num 0 byte 1 23 2 3 byte 2 byte 3 byte 4 byte 5 43 4 5 4 3 1 xmt fifo update xmt fifo empty serial in(rxd) start data(5-8) parity stop(1-2) rcv data ready rcv data ready intr serial in(rxd) rcv data ready intr s d p st 12 3 45 6 0 rcv fifo data num if fcr[4:3] == 2?h1 HMS30C7202 184 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 184 - 12.6 package 12.6.1 recommended soldering conditions 12.6.1.1 mqfp(metric quad flat pack ) type - recommended ip-reflow solder machine temperature 12.6.1.2 fbga(chip array ball grid array) type the soldering condition of fbga type package is the same as that of mqfp type package. - recommended ip-reflow solder machine temperature HMS30C7202 185 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 185 - 12.6.2 pictures of package marking package type 256fbga 256mqfp package marking hynix HMS30C7202 yyww . hynix HMS30C7202q yyww . HMS30C7202 186 ? 2002 hynix semiconductor inc. all rights reserved. version 1.4 - 186 - 13 appendix 13.1 deep-sleep, wake-up issues of HMS30C7202 pmu 13.1.1 wake-up HMS30C7202 has four external wa ke-up sources, and at least one of two power condition pins (pmadapok, pmbatok) should be high. mring (nuring), npmwakeup, rtc event can not be masked. pmu only has interrupt mask bits for interru pt controller. it means even though HMS30C7202 wake-up from deep-sleep, there might be no interru pt for interrupt controller. but every time, HMS30C7202 would wake up when any one of wake-up sources asserted. - wake-up sources mring : it?s connected nuring pin (?n? of nuring pin means ?low active?) this signal can not be masked in pmu. hotsync : hotsync condition or user defined co ndition (ex. plugging power adaptor) this signal is connected with gpiob[10] interrupt. nreset : nreset signal wake up from deep-sleep. npmwakeup : active low external signal. this signal can not be masked. rtc event : from rtc. this signal isn?t able to mask in pmu. all wake-up sources are filtered by debounce circuit (except rtc) with 250hz clock from rtc clock source, so if rtc clock stopped, wake-up sequence would not work. - needed condition for wake-up one of pmadapok and pmbatok should be high, it means there?s no power problem. if user wants to make wake-up regardless power source condition, set ?wakeup? bit of pmu mode register (pmumode) bit [3]. 13.1.2 deep-sleep - to go deep-sleep state, all wake-up conditions ar e cleared. if any wake-up pin stays in wake-up condition, 7202 would not go into ?deep-sleep mode?. - once deep-sleep mode is set (in slow mode) and no wake-up signal condition, state machine wait, until bus idle state. and after state machine jump into bus idle , in the very next ?bus access? operation, pmu get bus mastership from cpu and state machine keep going into deep-sleep mode through short sleep state. so metimes s/w need to wait until bus idle (ex. dma cases) and to prevent un-wanted next instruction execution after deep-sleep instruction set pmu mode register(pmumode), usually dummy loop is used for this purpose. - in some cases (in some s/w), to keep going in to deep-sleep, dummy bus (ex. just single read of a peripheral register) access is helpful after dummy loop. we think it is related with changing bus mastership. (or may need longer dum my loop) but we can?t sure it. |
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